Re: [gem5-users] Need clarification on estimateLatency() of DRAM

[biswabandan panda via gem5-users]

Hi,
      That was a bug.


On Fri, Jun 13, 2014 at 6:19 AM, Mostafa via gem5-users <gem5-users@gem5.org
> wrote:

> Anju M A <msd.anju <at> gmail.com> writes:
>
> >
> >
> >
> > Hello,
> > I have a doubt on a piece of code in esimateLatency() function in
> simple_dram.cc
> > The code snippet is like this :if (bank.openRow == dram_pkt->row) {
> >             rowHitFlag = true;            if (bank.freeAt < inTime)
> {               // CAS latency only               accLat +=
> tCL;               bankLat += tCL;            } else {
> >                 accLat += 0;                bankLat += 0;            }
> }
> >
> > My confusion is on the highlighted else block.
> >
> > If it is a row hit, and the bank is free at a later time compared to the
> inTime of the request, then why are both bankLatency and accessLatency set
> to zero?
> >
> > I feel the else block should have been this way :
> >
> > else {
> >            accLat += (bank.freeAt - inTime) + tCL;
> >
> >            bankLat += tCL;}
> >
> > Could someone please clarify this doubt?
> >
> >
> >
> >
> > -- Thanks & Regards,Anju
> >
> >
> >
> >
> >
> > _______________________________________________
> > gem5-users mailing list
> > gem5-users <at> gem5.org
> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
> Did you get an answer for your question ? I have the same doubts too.
>
> Regards
> Mostafa
>
>
> _______________________________________________
> gem5-users mailing list
> gem5-users@gem5.org
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>



-- 


*thanks&regards*
*BISWABANDAN*
http://www.cse.iitm.ac.in/~biswa/

“We might fall down, but we will never lay down. We might not be the best,
but we will beat the best! We might not be at the top, but we will rise.”

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