Thanks Anthony,
If we suppose that all instructions of a given application can be
entirely cached in i-cache, does the number of read request misses in
i-cache will correspond to the number of line fills in i-cache ? Also,
do you know how can I see in stats file if all instructions of the
application are entirely cached in L1 i-cache only, or if some
instructions are cached in L1 i-cache and others are cached in L2 ?
If i am not wrong, in the first case, read misses in i-cache will
correspond to compulsory cache misses which will occur only at the
beginning of the execution. Whereas in the second case, some read misses
will occur during the execution (not only at the beginning).
For instance, I have simulated the benchmark BARNES of SPLASH-2 in FS
mode with --caches and --l2cache options. In stats file, I can see that
results :
system.physmem.num_reads::cpu.inst 22321
system.l2.overall_misses::cpu.inst 22321
system.cpu.icache.ReadReq_misses::cpu.inst 98236
Does it mean that instructions of the application is not entirely cached
in L1 i-cache ?
Cordialement / Best Regards
SENNI Sophiane
Ph.D. candidate - Microelectronics
LIRMM - www.lirmm.fr
Le 08/03/2014 15:28, Anthony Gutierrez a écrit :
In most CPUs the i-cache is read only. Nothing should be explicitly
written to the i-cache, it will be populated when a fetch req misses,
causing a line fill. Even in self-modifying code you don't write
explicitly to an executable page, you first remove execute permissions
and mark it as data.
Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier
<http://web.eecs.umich.edu/%7Eatgutier>
On Sat, Mar 8, 2014 at 9:23 AM, senni sophiane
<[email protected] <mailto:[email protected]>> wrote:
Hi everybody,
In stats file, I can find "dcache.WriteReq_accesses" corresponding
to the number of write request accesses in D-Cache. However, there
is no such results for I-Cache. As far as I know, a number of
writes has to occur to cache instructions of the application from
Main Memory to I-Cache. So, am I missing something ? Or are there
other results in stats file that can inform us about I-Cache write
accesses ?
Thanks
--
Cordialement / Best Regards
SENNI Sophiane
Ph.D. candidate - Microelectronics
LIRMM - www.lirmm.fr <http://www.lirmm.fr>
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