Hello,
I have been working a Ruby cache coherence protocol over the past few months. I
have it completed and I am just debugging it now. I am trying to boot the Linux
Kernel in a 16-core Alpha system. The problem I am having is the 15th and 16th
CPU cores are not initializing. I noticed in the tracing debug output that the
CPUs seem to continually fetch the same memory address afterwards (0x15e40).
The system never reaches a deadlock as all of the memory requests are completed.
I am guessing that the problem is that the data is lost when it is going from
one L1Cache to another through the memory system. I am assuming that my cache
coherence algorithms may accidentally write a incorrect data black into the
cache memory instead of the proper one. In order to check if this is a problem,
I need to somehow check if the L1 Cache is getting the correct data. I am
wondering if anybody here has any suggestions how I can do it.
Best regards,
Alex
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