Hi all, I'm working on modify some parts of inorder pipline to extend X86 ISA. I add an pseudo instruction, which is similar to load, and its load address is passed as input register and stored in register rdi. I'm confused that how to decode the address stored in rdi as effective address. I found that in the pipeline_traits.5stage.cc, if the instruction is memref, AGENUnit will generate effective address. In execute function of AGENUnit it call inst->calcEA(), and in calcEA(), it calls this->staticInst->eaComp(this, this->traceData). However, I didn't find where eaComp is defined. Am I on the right track? Anyone can give me some suggestions?
Thanks. With respects, Xiaoyu Zheng
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