Hi all, I am using atomic cpu and i've set memory latency to 0 and I am only using L1 cache with hit latency of 1. I am running a simulation for 1 second (1 billion cycles).
I am assuming that each instruction or micro-ops (i'm using X86) would take 1 cycle to complete, is this correct? Because if that's true, then I expect that the total number of simulated ops to be 1 billion since I'm simulating for 1 billion cycles. However, in the stats file I am seeing something like 800+ million simulated micro-ops….can someone explain why there is a difference? Many Thanks, Jack _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
