Thanks Malek for the clarification. I can see that in the recent version total number of accesses are also reported along with the misses and hits. So, by dumping periodically and then calculating the absolute numbers out of cumulative values, we can get miss/hit rate for each interval.
Thanks. On Wed, Jun 12, 2013 at 3:19 PM, Malek Musleh <malek.mus...@gmail.com>wrote: > Hi Mahshid, > > It uses gem5's stats package, which are opaque variables (only computed > should never be read) and printed out when dump_stats is called -- either > by the psuedo instruction or at the end of the simulation. > > There is a gem5_reset_stats() psuedo instruction that resets all the gem5 > stats, and there is a dump_reset_stats() instruction that can be used to > dump the stats, and then reset to 0 for a fixed period interval. > > I think the dump_reset_stats is what you want, but using it will also > reset all the other stats. > > Malek > > > On Wed, Jun 12, 2013 at 1:44 PM, Mahshid Sedghi > <mahshid.sed...@gmail.com>wrote: > >> Hi Malek, >> >> Thanks a lot for the update. I will get the recent revision. Does this >> revision calculate cache miss rates periodically when dumping stats >> periodically? >> >> And about my calculation, I actually sum up L1 misses across all L1 >> caches and consider this to be overall L2 accesses. In fact I am >> calculating the average L2 miss rate and since my L2 is shared among all >> cores, I look at it as a big shared L2 cache. >> >> Thanks, >> Mahshid >> >> >> >> >> On Wed, Jun 12, 2013 at 1:04 PM, Malek Musleh <malek.mus...@gmail.com>wrote: >> >>> The patch was incorporated into some other recent ruby stat changes >>> recently (1-2 weeks): specifically the removal of the cache profiler, and >>> the counting of hits/misses directly in the sm file. So you should probably >>> update. >>> >>> The other thing is, I think your complicating your calculations a bit: >>> >>> L2 miss rate = 100*(total L2 misses for all L2 banks) / (total L1 Dcache >>> misses+total L1 Icache misses) >>> >>> Specifically, how are you going to access an L1 cache miss count/rate >>> from an L2 cache in the code? You should just stick to basics when thinking >>> about rates (%/total%): Whenever a request comes from L1port to L2 cache, >>> it is an access, and when that access "misses" (the request has to be >>> forwarded/sent up to directory) it is a miss type. >>> >>> Malek >>> >>> >>> >>> On Wed, Jun 12, 2013 at 12:51 PM, Mahshid Sedghi < >>> mahshid.sed...@gmail.com> wrote: >>> >>>> Thanks for your reply Maxime. But is there anything wrong with the way >>>> I calculate the rates? I see that the patch has been submitted for review >>>> long time back, but has not been applied to the gem5 release yet. Is this >>>> patch reliable? >>>> >>>> Thanks. >>>> Mahshid >>>> >>>> >>>> On Wed, Jun 12, 2013 at 7:29 AM, Maxime Chéramy < >>>> maxime.cher...@gmail.com> wrote: >>>> >>>>> Have a look to http://reviews.gem5.org/r/1467/ but the support of >>>>> MESI_CMP is not correct, you'll have to do some changes. >>>>> >>>>> 2013/6/12 Mahshid Sedghi <mahs...@cse.psu.edu> >>>>> >>>>>> Hi all, >>>>>> >>>>>> I'm trying to calculate L1 and L2 cache miss rates for a full system >>>>>> simulation using ruby (MESI_CMP_directory) + garnet. I dump stats >>>>>> periodically to get the trend of the rates. I can see that in ruby.stats, >>>>>> total_misses for each L1 and L2 cache bank is reported. Also, I can see >>>>>> the >>>>>> events which are happening inside the coherency protocol. So, I use the >>>>>> total "Load" and "Store" counts and calculate the miss rates as the >>>>>> following: >>>>>> >>>>>> L1 Dcache miss rate = 100* (total L1D misses for all L1D caches) >>>>>> /(Loads+Stores) >>>>>> >>>>>> L2 miss rate = 100*(total L2 misses for all L2 banks) / (total L1 >>>>>> Dcache misses+total L1 Icache misses) >>>>>> >>>>>> But for some reason, the rates I am getting does not make sense. I >>>>>> was wondering if this is the right way to calculate the miss rates using >>>>>> ruby statistics. >>>>>> >>>>>> I appreciate any help. >>>>>> Mahshid >>>>>> >>>>>> _______________________________________________ >>>>>> gem5-users mailing list >>>>>> gem5-users@gem5.org >>>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>>>> >>>>> >>>>> >>>>> _______________________________________________ >>>>> gem5-users mailing list >>>>> gem5-users@gem5.org >>>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>>> >>>> >>>> >>>> _______________________________________________ >>>> gem5-users mailing list >>>> gem5-users@gem5.org >>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>>> >>> >>> >>> _______________________________________________ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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