Hello,

Merci Fernando !

If anybody have more some idea or solution for my problem, don't hesitate
to tell me :-)


Thank you in  advance


2013/5/30 Fernando Endo <[email protected]>

> My guess is 'src/arch/mips/', but I have no idea how it works...
>
> Boa sorte!
>
> Fernando
>
> --
> Fernando A. Endo, PhD student and researcher
>
> Université de Grenoble, UJF
> France
>
>
>
> 2013/5/30 Andrws Vieira <[email protected]>
>
>> Hi,
>>
>>
>> To extract the information of time or cycles GEM5 I don't have problems,
>> but I do not know for where to start, if I start changing a ready ISA
>> (e.g. MIPS) or start one from the beginning ?
>>
>>
>> Thanks
>>
>>
>> 2013/5/30 Fernando Endo <[email protected]>
>>
>>> Hi,
>>>
>>> Note that I've never worked with it, so what I'm saying can be
>>> completely wrong, but in my opinion, if you're interested in timing
>>> information you can use the timing model of cpu to simulate your new
>>> instructions. The fuctional behavior and the timing info will be defined by
>>> the your ISA (I think).
>>>
>>> Of course you'll have to find a good way to estimate how fast your new
>>> processor can execute them. If you say your instructions can compute a
>>> matrix multiplication in one cycle, you will need good arguments to say so!
>>> Otherwise your processor may simply be unfeasible.
>>>
>>> If you're proposing a new uarch, them you'll probably need to modify the
>>> pipelined cpu models.
>>>
>>> Hope it helps,
>>>
>>> Fernando
>>>
>>> --
>>> Fernando A. Endo, PhD student and researcher
>>>
>>> Université de Grenoble, UJF
>>> France
>>>
>>>
>>>
>>> 2013/5/30 Andrws Vieira <[email protected]>
>>>
>>>> Hello Fernando,
>>>>
>>>> I dont know, is possible to do both ? If yes, what can be the better
>>>> way ?
>>>>
>>>> I was thinking in modify the instructions set, because I know what
>>>> algorithms that will run ...
>>>> For example, matrix multiplication, in this case I was thinking of
>>>> doing only two instructions (LoadMatrix and MultMatrix)
>>>>
>>>> What do you suggest me?
>>>>
>>>>
>>>> Thank You in Advance,
>>>>
>>>>
>>>> 2013/5/29 Fernando Endo <[email protected]>
>>>>
>>>>> Hi,
>>>>>
>>>>> Do you want to modify/adapt the existing cpu models to your
>>>>> architecture or just to implement a new ISA?
>>>>>
>>>>> Regards,
>>>>>
>>>>> Fernando
>>>>>
>>>>> --
>>>>> Fernando A. Endo, PhD student and researcher
>>>>>
>>>>> Université de Grenoble, UJF
>>>>> France
>>>>>
>>>>>
>>>>>
>>>>> 2013/5/26 Andrws Vieira <[email protected]>
>>>>>
>>>>>>  Hello everybody,
>>>>>>
>>>>>>
>>>>>> I need to make an architecture/organization that shows be more
>>>>>> efficient (in some benchmarks) for example that the MIPS.
>>>>>>
>>>>>> Is possible I make a organization (ISA for gem5), for example with
>>>>>> few and simple instructions and be able to compile an C code for this my
>>>>>> architecture ?
>>>>>>
>>>>>> Thanks in advance
>>>>>>
>>>>>> --
>>>>>> *Andrws Aires Vieira       *
>>>>>> Mestrando em Computação
>>>>>> Universidade Federal do Rio Grande do Sul - UFRGS
>>>>>>
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>>>>>>
>>>>>
>>>>>
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>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> *Andrws Aires Vieira       *
>>>> Mestrando em Computação
>>>> Universidade Federal do Rio Grande do Sul - UFRGS
>>>>
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>>
>>
>>
>> --
>> *Andrws Aires Vieira       *
>> Mestrando em Computação
>> Universidade Federal do Rio Grande do Sul - UFRGS
>>
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-- 
*Andrws Aires Vieira       *
Mestrando em Computação
Universidade Federal do Rio Grande do Sul - UFRGS
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