Thanks Andreas
This was of great help. Now I am getting consistent results.
On Wed, Feb 27, 2013 at 11:53 PM, Andreas Hansson
<andreas.hans...@arm.com>wrote:
> Hi Shivam,
>
> You have connected the CPU directly to the L3bus in your connectAllPorts
> call. Thereby you have bypassed the L2 completely and thus the absence of
> stats.
>
> Have a look at the config.dot.pdf in m5out. If it's not there, make sure
> you have py-dot installed. The dot diagram will show you what your system
> looks like and what ports are connected together (to avoid further
> mistakes).
>
> You actually do not need a toL3bus at all. You can simply put the L3
> between the membus and the DRAM controller.
>
> Good luck.
>
> Andreas
>
> From: Tao Zhang <tao.zhang.0...@gmail.com>
> Reply-To: gem5 users mailing list <gem5-users@gem5.org>
> Date: Wednesday, 27 February 2013 18:08
> To: gem5 users mailing list <gem5-users@gem5.org>
> Subject: Re: [gem5-users] Unexpected results on addition of L3 Cache in
> Classic Memory Model
>
> Hi Shivam,
>
> It seems weird since L2 reports should have been there. How did you
> declare your L3Cache() and l2_cache_class()? Did you see both "l2" and "l3"
> in m5out/config.ini?
>
> -Tao
>
> On 02/27/2013 12:58 PM, Shivam Agarwal wrote:
>
> Hello all
>
> I have incorporated an L3 cache in configs/common/CacheConfig.py as
> follows:
> if options.l2cache:
> system.l2 = l2_cache_class(clock=options.clock,
> size=options.l2_size,assoc=options.l2_assoc,
> block_size=options.cacheline_size)
> system.tol2bus = CoherentBus(clock = options.clock, width = 32)
> if options.l3cache:
> system.tol3bus = CoherentBus(clock = options.clock, width = 32)
> system.l2.cpu_side = system.tol2bus.master
> system.l2.mem_side = system.tol3bus.slave
> system.l3 = L3Cache(size = options.l3_size, assoc =
> options.l3_assoc, block_size=options.cacheline_size)
> system.l3.cpu_side = system.tol3bus.master
> system.l3.mem_side = system.membus.slave
> else:
> system.l2.mem_side = system.membus.slave
> system.l2.cpu_side = system.tol2bus.master
>
> ----------some code which I have not changed------
>
> if options.l2cache and options.l3cache :
> system.cpu[i].connectAllPorts(system.tol3bus, system.membus)
> elif options.l2cache and not options.l3cache:
> system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
> else:
> system.cpu[i].connectAllPorts(system.membus)
>
> I ran the following commands:
> 1) ./build/ARM/gem5.opt --debug-flags=DRAM configs/example/se.py -c
> queens -o 8 --caches --l2cache --l1d_size=1kB --l1i_size=1kB *
> --l2_size=2MB*
>
> system.l2.overall_misses::total 591
> system.physmem.num_reads::total 591
>
> 2) ./build/ARM/gem5.opt --debug-flags=DRAM configs/example/se.py -c queens
> -o 8 --caches --l2cache --l1d_size=1kB --l1i_size=1kB *--l2_size=2kB*
>
> system.l2.overall_misses::total 1081
> system.physmem.num_reads::total 1081
>
> For these cases, the results seem to be consistent as the overall misses
> increases with decreasing L2 size and these go to physmem(which is DRAM in
> this case) for further servicing. According to my understanding if I insert
> an L3 cache between L2 and Physmem then L2 misses should not change and
> should be served by L3.
> *Problem 1*) After the incorporation of L3 cache I am not able to see L2
> misses ("system.l2.overall_misses::total ") anymore, and only L3 misses are
> reported in stats.txt file. How can I see L2 misses?*
> Problem2) *Whatever be the size of L2 cache, number of misses at L3 are
> constant.
>
> 3)./build/ARM/gem5.opt --debug-flags=DRAM configs/example/se.py -c queens
> -o 8 --caches --l2cache --l3cache --l1d_size=1kB --l1i_size=1kB *--l2_size=2MB
> --l3_size=1MB*
> system.physmem.num_reads::total 591
> system.l3.overall_misses::total 591
>
> 4)./build/ARM/gem5.opt --debug-flags=DRAM configs/example/se.py -c queens
> -o 8 --caches --l2cache --l3cache --l1d_size=1kB --l1i_size=1kB*--l2_size=2kB
> --l3_size=1MB
> *
> system.physmem.num_reads::total 591
> system.l3.overall_misses::total 591
>
> I would like to see misses occuring at every level of memory hierarchy.
> Kindly help me about how to do this.
>
> Best Regards
> Shivam Agarwal
> Student, IIT-Delhi
>
>
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