I've got a long outstanding todo to add a Wiki page on the CommMonitor.
In this case, if you insert a CommMonitor at the point where you want a trace
(between the L2 and the membus I would imagine), and then give this CommMonitor
a trace_file="myaccesstrace.trc.gz" or similar, you will get a complete trace
encoded using protobufs (see the packet.proto in src/proto).
Andreas
From: Amin Farmahini <[email protected]<mailto:[email protected]>>
Reply-To: gem5 users mailing list
<[email protected]<mailto:[email protected]>>
Date: Wednesday, 13 February 2013 19:32
To: gem5 users mailing list <[email protected]<mailto:[email protected]>>
Cc: "[email protected]<mailto:[email protected]>"
<[email protected]<mailto:[email protected]>>
Subject: Re: [gem5-users] How to obtain a cycle accurate trace of L1 and L2
cache misses
You can use debug (trace) flags. Try --debug-flags=Cache. This should give you
cache misses and their missed addresses as well as more information on cache
access.
You may want to define your own flag to specifically generate what you need.
Thanks,
Amin
On Tue, Feb 12, 2013 at 8:56 PM, Shivam Agarwal
<[email protected]<mailto:[email protected]>> wrote:
Hello
I wish to obtain the cycle accurate trace of cache misses along with the
missed address (for alpha cpu).
Kindly provide me with suggestions about how to do the same.
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