Hi all,
This is probably a dumn question but what should I do before instantiating
m5? I was going over tutorials, and tried to create a simple simulation
script. The error message I have is;
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command line: ./build/X86/gem5.opt --debug-flags=Cache
--trace-file=my_trace.out configs/example/hardcoded.py -c
tests/test-progs/queens/bin/x86/linux/queens -o -c 8 --caches --l2cache
--cpu-type=timing
Global frequency set at 1000000000000 ticks per second
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/home/matara/Apps/gem5-e71f71ce233a/src/python/m5/main.py", line
359, in main
exec filecode in scope
File "configs/example/hardcoded.py", line 46, in <module>
m5.instantiate()
File "/home/matara/Apps/gem5-e71f71ce233a/src/python/m5/simulate.py",
line 106, in instantiate
for obj in root.descendants(): obj.createCCObject()
File "/home/matara/Apps/gem5-e71f71ce233a/src/python/m5/SimObject.py",
line 1040, in createCCObject
self.getCCObject() # force creation
File "/home/matara/Apps/gem5-e71f71ce233a/src/python/m5/SimObject.py",
line 1025, in getCCObject
self._ccObject = params.create()
AttributeError: 'MemObjectParams' object has no attribute 'create'
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I copied my script mostly from Hipeac conference slides in tutorials;
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import m5
from m5.objects import *
from m5.params import VectorSlavePort, VectorMasterPort
class L1Cache(BaseCache):
assoc = 2
block_size = 64
mshrs = 10
tgts_per_mshr = 5
is_top_level = True
class L2Cache(BaseCache):
assoc = 8
block_size = 128
mshrs = 10
tgts_per_mshr = 5
class Bus(MemObject):
slave = VectorSlavePort("vector port for connecting masters")
master = VectorMasterPort("vector port for connecting slaves")
cpu = TimingSimpleCPU(cpu_id = 0)
cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'),
L1Cache(size='256kB'),
L2Cache(size='2MB'))
system = System(cpu = cpu,
physmem = SimpleMemory(),
membus=Bus())
process = LiveProcess()
process.executable = 'hello'
# root.system.cpu.workload = LiveProcess(cmd = 'hello’, executable =
binpath('hello'))
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz'
root = Root(full_system=False, system = system)
# instantiate configuration
m5.instantiate()
# simulate until program terminates
exit_event = m5.simulate(m5.MaxTick)
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Do you have any pointers?
Thanks for your time.
Mehmet
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