I am doing something wrong here. What I an trying to do is create 4 CPUS
with different frequencies. I am passing --num-cpus=1 because I want 4
different. Please take a look.
import optparse
import sys
import m5
from m5.defines import buildEnv
from m5.objects import *
from m5.util import addToPath, fatal
addToPath('../common')
from FSConfig import *
from SysPaths import *
from Benchmarks import *
import Simulation
import CacheConfig
from Caches import *
import Options
parser = optparse.OptionParser()
Options.addCommonOptions(parser)
Options.addFSOptions(parser)
(options, args) = parser.parse_args()
if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
# driver system CPU is always simple... note this is an assignment of
# a class, not an instance.
DriveCPUClass = AtomicSimpleCPU
drive_mem_mode = 'atomic'
# system under test can be any CPU
(CPUClass1, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
(CPUClass2, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
(CPUClass3, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
(CPUClass4, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
(DriveCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(
options)
TestCPUClass.clock = '2GHz'
DriveCPUClass.clock = '3GHz'
CPUClass1=AtomicSimpleCPU
CPUClass2=AtomicSimpleCPU
CPUClass3=AtomicSimpleCPU
CPUClass4=AtomicSimpleCPU
CPUClass1.clock='3GHz'
CPUClass2.clock='2GHz'
CPUClass3.clock='3GHz'
CPUClass4.clock='1GHz'
if options.benchmark:
try:
bm = Benchmarks[options.benchmark]
except KeyError:
print "Error benchmark %s has not been defined." % options.benchmark
print "Valid benchmarks are: %s" % DefinedBenchmarks
sys.exit(1)
else:
if options.dual:
bm = [SysConfig(disk=options.disk_image,
mem=options.mem_size), SysConfig(disk=options.disk_image,
mem=options.mem_size)]
else:
bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
np = options.num_cpus
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode,
options.machine_type, bm[0],
bare_metal=options.bare_metal)
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
test_sys.init_param = options.init_param
test_sys.cpu = [CPUClass1(cpu_id=i) for i in xrange(np)]
test_sys.cpu = [CPUClass2(cpu_id=i) for i in xrange(np)]
test_sys.cpu = [CPUClass3(cpu_id=i) for i in xrange(np)]
test_sys.cpu = [CPUClass4(cpu_id=i) for i in xrange(np)]
if bm[0]:
mem_size = bm[0].mem()
else:
mem_size = SysConfig().mem()
if options.caches or options.l2cache:
test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range])
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [test_sys.physmem.range])
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem and (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.checker:
test_sys.cpu[i].addCheckerCpu()
CacheConfig.config_cache(options, test_sys)
if len(bm) == 2:
if buildEnv['TARGET_ISA'] == 'alpha':
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'mips':
drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'sparc':
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'x86':
drive_sys = makeX86System(drive_mem_mode, np, bm[1])
elif buildEnv['TARGET_ISA'] == 'arm':
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=4)
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
if options.fastmem:
drive_sys.cpu.fastmem = True
if options.kernel is not None:
drive_sys.kernel = binary(options.kernel)
drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [drive_sys.physmem.range])
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave
drive_sys.init_param = options.init_param
root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
elif len(bm) == 1:
root = Root(full_system=True, system=test_sys)
else:
print "Error I don't know how to create more than 2 systems."
sys.exit(1)
if options.timesync:
root.time_sync_enable = True
if options.frame_capture:
VncServer.frame_capture = True
Simulation.setWorkCountOptions(test_sys, options)
Simulation.run(options, root, test_sys, FutureClass)
On Thu, Nov 8, 2012 at 4:58 PM, Marko Zivkovic <mzivk...@hawk.iit.edu>wrote:
> Thank you. Can you explain to me how to set up different freq to different
> CPUs?
>
> I tried with --clock but I can not specify different CPUs. In fs.py
> couldn't find the way how to do it too.
>
>
>
>
> On Wed, Nov 7, 2012 at 10:32 AM, Nilay Vaish <ni...@cs.wisc.edu> wrote:
>
>> On Tue, 6 Nov 2012, Marko Zivkovic wrote:
>>
>> The difference should be the communication latency between cores vs
>>> CPUs, synchronization in cache memory between cores vs CPUs... Currently
>>> I
>>> can pass --num-cpu but I would like heterogeneous setup( cores of CPUs
>>> with
>>> different frequencies). Currently I am using slightly modified fs.py with
>>> only one CPU freq setting.
>>>
>>>
>> You can set frequency for each of the cpus to a different value. And you
>> can set the communication latencies to what you feel are reasonable for a
>> multi-core system. You do not require any new configuration files. You just
>> need to set the parameters as per your requirements.
>>
>> --
>> Nilay
>>
>
>
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
