Hi Mir, I am not quite sure what the issue is here? As I said I ran the InOrderCPU with Ruby Memory Model (MESI Protocol) for SPEC2k6 benchmarks (not publicly available). You can run this setup with any benchmark you like.
E.g. HelloWorld ./build/ALPHA_MESI_CMP_directory/m5.opt -r -d ./m5out/ ./configs/example/se.py --ruby --caches --cpu-type=inorder --caches -c ./tests/test-progs/hello/bin/alpha/linux/hello You just have to remove the fatal from ./configs/example/se.py that says Ruby requires TimingSimple or O3. Malek On Wed, Oct 31, 2012 at 12:00 PM, mir shan <mirsh...@yahoo.com> wrote: > > Hi Malek > can u write the commands which you used in this process. > > regards > Mir > * > * > > > --- On *Fri, 12/10/12, Malek Musleh <malek.mus...@gmail.com>* wrote: > > > From: Malek Musleh <malek.mus...@gmail.com> > Subject: Re: [gem5-users] [gem5-dev] Status Matrix for Ruby SE InOrderCPU > To: "Nilay Vaish" <ni...@cs.wisc.edu> > Cc: "gem5 users mailing list" <gem5-users@gem5.org> > Date: Friday, 12 October, 2012, 7:53 PM > > Ok, allow me to clarify. > > I tested using the ALPHA_MESI_CMP_directory protocol, using the > default topology=CrossBar, and running the reference inputs for 500 > million instructions, the simulation seems to go on fine (no > errors/early terminations). Some of the benchmarks do not generate > output until the benchmark itself completes, but for the ones that do > generate intermediate output (e.g. bzip2) the outputs did match. > > I also, ran a couple of the benchmarks using the test input as opposed > to the ref, so I that I can run them until completion, and program > output is correct (otherwise what would be the point?). > > The only trouble I have had so far, is with a particular benchmark > itself, but I believe its an issue due to the program itself and not > the simulator. The following error is generated with respect to the > SimpleTimingCPU. > > /home/musleh/SPEC2k6/benchspec/CPU2006/403.gcc/data/test/input/cccp.i:3121: > unable to find a register to spill in class `SIREG' > /home/musleh/SPEC2k6/benchspec/CPU2006/403.gcc/data/test/input/cccp.i:3121: > this is the insn: > /home/musleh/SPEC2k6/benchspec/CPU2006/403.gcc/data/test/input/cccp.i:3121: > confused by earlier errors, bailing out > > Hence, in any case, as far as the InOrderCPU goes for ALPHA+RUBY+SE > Mode, things seem to contradict what is listed in the status matrix. > > As I said before, I have not tested multiprogrammed workloads, because > I don't see how that would be any different if each CPU is assigned a > different workload. I also have not tested the different Ruby > Protocols yet, but if there would be an issue with this simulation > combo, I would be guessing it would be with the CPU Model and not the > Protocol because AFAIK ALPHA+RUBY+O3+FS works for some changeset in > the main tree and that is much harder to get working/more likely to > have issues than running in SE Mode. > > > Malek > > On Thu, Oct 11, 2012 at 9:25 PM, Nilay Vaish > <ni...@cs.wisc.edu<http://mc/compose?to=ni...@cs.wisc.edu>> > wrote: > > On Thu, 11 Oct 2012, Malek Musleh wrote: > > > >> Hi, > >> > >> According to the status matrix: http://www.m5sim.org/Status_Matrix it > >> says that it is unknown whether or not the InOrderCPU Modelm works for > >> SE Mode + Ruby Memory Model. > >> > >> I have ran several SPEC2k6 benchmarks (~500 million instructions), > >> single core using the MESI_CMP_directory protocol, and it seems to > >> work fine. I had to make a small change to the config script in order > >> to avoid a fatal() call, but other than that, there was nothing else > >> that I could see as being an issue. > >> I have not tested multi-programmed workloads, but that should not > >> matter as long as each workload is assigned to a different CPU. > >> > >> Are there any particular issues known for this setup? I know that FS > >> Support for InOrder is not quite there yet? > >> > >> > > > > Did you check the final output? You failed to mention the architecture > you > > are using and the mail should have been sent to gem5-users list. > > > > -- > > Nilay > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org <http://mc/compose?to=gem5-users@gem5.org> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > >
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