Thanks for the confirmation. I'll look into it and discuss potential solutions.
BTW, just curious, is there any particular reason for putting the code for fetch in a .hh, instead of a .cc file? Thanks! Runjie On Fri, Oct 26, 2012 at 3:42 PM, Nilay Vaish <ni...@cs.wisc.edu> wrote: > I understand now the problem that you are trying to elucidate. I just > checked the fetch_impl.hh. If you look at line 889, it is doing exactly > what you have suggested. It might be that there is some thing wrong with > this code and it is not behaving as expected. You might want to take a > deeper dive in to the fetch stage's code and figure out the reason why the > icache access was not issued a cycle earlier. > > -- > Nilay > > > On Thu, 25 Oct 2012, Runjie Zhang wrote: > > Sorry for the confusion. >> >> The numbers 60, 65 and 70 were part of the tick number each cycle >> started. I >> removed some digits in the tick count to make each line shorter... >> >> The complete trace looks like this: >> >> 33922322296000: system.switch_cpus.fetch: Running stage. >> 33922322296000: system.switch_cpus.fetch: Attempting to fetch from [tid:0] >> 33922322296000: system.switch_cpus.fetch: [tid:0]: Adding instructions to >> queue to decode. >> 33922322296000: system.switch_cpus.fetch: [tid:0]: Instruction PC 0x400ab7 >> (0) created [sn:5050]. >> 33922322296000: system.switch_cpus.fetch: [tid:0]: Instruction is: >> ADD_R_R : add ecx, ecx, esi >> 33922322296000: system.switch_cpus.fetch: [tid:0]: Instruction PC 0x400ab9 >> (0) created [sn:5051]. >> 33922322296000: system.switch_cpus.fetch: [tid:0]: Instruction is: >> ADD_R_R : add edx, edx, esi >> 33922322296000: system.switch_cpus.fetch: [tid:0]: Instruction PC 0x400abb >> (0) created [sn:5052]. >> 33922322296000: system.switch_cpus.fetch: [tid:0]: Instruction is: >> SUB_R_R : sub eax, eax, esi >> 33922322296000: system.switch_cpus.fetch: [tid:0]: Instruction PC 0x400abd >> (0) created [sn:5053]. >> 33922322296000: system.switch_cpus.fetch: [tid:0]: Instruction is: >> SUB_R_R : sub ebx, ebx, esi >> 33922322296000: system.switch_cpus.fetch: [tid:0]: Done fetching, reached >> fetch bandwidth for this cycle. >> >> 33922322296500: system.switch_cpus.BPredUnit: BranchPred: [tid:0]: >> Committing branches until [sn:5025]. >> 33922322296500: system.switch_cpus.fetch: Running stage. >> 33922322296500: system.switch_cpus.fetch: Attempting to fetch from [tid:0] >> 33922322296500: system.switch_cpus.fetch: [tid:0]: Adding instructions to >> queue to decode. >> 33922322296500: system.switch_cpus.fetch: [tid:0]: Issuing a pipelined >> I-cache access, starting at PC (0x400abf=>0x400ac7).(0=>1). >> 33922322296500: system.switch_cpus.fetch: [tid:0] Fetching cache line >> 0x400ac0 for addr 0x400ac0 >> 33922322296500: system.switch_cpus.fetch: Fetch: Doing instruction read. >> 33922322296500: system.switch_cpus.fetch: [tid:0]: Doing Icache access. >> 33922322297000: system.switch_cpus.fetch: [tid:0] Waking up from cache >> miss. >> 33922322297000: system.switch_cpus.BPredUnit: BranchPred: [tid:0]: >> Committing branches until [sn:5029]. >> 33922322297000: system.switch_cpus.fetch: Running stage. >> 33922322297000: system.switch_cpus.fetch: Attempting to fetch from [tid:0] >> 33922322297000: system.switch_cpus.fetch: [tid:0]: Icache miss is >> complete. >> 33922322297000: system.switch_cpus.fetch: [tid:0]: Adding instructions to >> queue to decode. >> 33922322297000: system.switch_cpus.fetch: [tid:0]: Instruction PC 0x400abf >> (0) created [sn:5054]. >> 33922322297000: system.switch_cpus.fetch: [tid:0]: Instruction is: >> SUB_R_R : sub ecx, ecx, esi >> 33922322297000: system.switch_cpus.fetch: [tid:0]: Instruction PC 0x400ac1 >> (0) created [sn:5055]. >> 33922322297000: system.switch_cpus.fetch: [tid:0]: Instruction is: >> SUB_R_R : sub edx, edx, esi >> 33922322297000: system.switch_cpus.fetch: [tid:0]: Instruction PC 0x400ac3 >> (0) created [sn:5056]. >> 33922322297000: system.switch_cpus.fetch: [tid:0]: Instruction is: >> ADD_R_R : add eax, eax, esi >> 33922322297000: system.switch_cpus.fetch: [tid:0]: Instruction PC 0x400ac5 >> (0) created [sn:5057]. >> 33922322297000: system.switch_cpus.fetch: [tid:0]: Instruction is: >> ADD_R_R : add ebx, ebx, esi >> 33922322297000: system.switch_cpus.fetch: [tid:0]: Done fetching, reached >> fetch bandwidth for this cycle. >> >> 33922322297500: system.switch_cpus.BPredUnit: BranchPred: [tid:0]: >> Committing branches until [sn:5033]. >> 33922322297500: system.switch_cpus.fetch: Running stage. >> 33922322297500: system.switch_cpus.fetch: Attempting to fetch from [tid:0] >> 33922322297500: system.switch_cpus.fetch: [tid:0]: Adding instructions to >> queue to decode. >> 33922322297500: system.switch_cpus.fetch: [tid:0]: Instruction PC 0x400ac7 >> (0) created [sn:5058]. >> 33922322297500: system.switch_cpus.fetch: [tid:0]: Instruction is: >> ADD_R_R : add ecx, ecx, esi >> 33922322297500: system.switch_cpus.fetch: [tid:0]: Instruction PC 0x400ac9 >> (0) created [sn:5059]. >> 33922322297500: system.switch_cpus.fetch: [tid:0]: Instruction is: >> ADD_R_R : add edx, edx, esi >> 33922322297500: system.switch_cpus.fetch: [tid:0]: Instruction PC 0x400acb >> (0) created [sn:5060]. >> 33922322297500: system.switch_cpus.fetch: [tid:0]: Instruction is: >> SUB_R_R : sub eax, eax, esi >> 33922322297500: system.switch_cpus.fetch: [tid:0]: Instruction PC 0x400acd >> (0) created [sn:5061]. >> 33922322297500: system.switch_cpus.fetch: [tid:0]: Instruction is: >> SUB_R_R : sub ebx, ebx, esi >> 33922322297500: system.switch_cpus.fetch: [tid:0]: Done fetching, reached >> fetch bandwidth for this cycle. >> >> Sorry for the confusion. >> >> Runjie >> >> >>
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