Hi Sami, Do you want to use the same cache for Instructions and Data? If so, place a CoherentBus between the CPU ports and the cache, connect the CPU .inst and .data to the bus.slave, then the bus.master to the cache.cpu_side.
Good luck. Andreas From: "M.Sami Dikici" <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Sunday, 21 October 2012 23:28 To: "[email protected]<mailto:[email protected]>" <[email protected]<mailto:[email protected]>> Subject: [gem5-users] shared L1 cache hello everyone, i need to implement shared L1 by using Gem5 but i could not do it properly according to the hints which i found in the mail-list. if you don't mind, can anybody help me to do that i am new at gem5 and i need some detailed help. Thank you to spend your time by reading this. good luck at your researches. Best Regards Sami -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
