Hey,
In my quest of inorder pipeline I've encountered another problem. I run two threads on a switch on cache miss machine. Also. as opposed to other question I've sent so far, I'm using the 5 stages pipeline supplied with the simulator. The Frequency is 2Ghz and I set the cache latency to be 800ps (which is more than a clock cycle). Now. In the fourth stage memory request is being sent and in the fifth stage the cache is being read. I get the following: 159888500: system.cpu.stage4: [tid:0]: Not blocked, so attempting to run stage. 159888500: system.cpu.stage4: [tid:0]: Processing instruction [sn:41180] ldq with PC (0x1200003f0=>0x1200003f4) 159888500: system.cpu.stage4: [tid:0]: [sn:41180]: sending request to system.cpu.dcache_port. 159888500: system.cpu.dcache_port: [tid:0]: [sn:41180]: Updating the command for this instruction 159888500: system.cpu.dcache_port: [tid:0]: [sn:41180]: Trying to Complete Data Read Access 159888500: system.cpu.dcache_port: STALL: [tid:0]: Data miss from 0x12009ed78 159888500: system.cpu.stage4: [tid:0]: [sn:41180] request to system.cpu.dcache_port failed. 159888500: system.cpu.stage4: [tid:0] [sn:41180] Detected cache miss. 159888500: system.cpu.stage4: Inserting [tid:0][sn:41180] into switch out buffer. 159888500: system.cpu: Scheduling CPU Event (SquashFromMemStall) for cycle 159888500, [tid:0]. 159888500: system.cpu.ResourcePool: Ignoring Unrecognized CPU Event (SquashFromMemStall). 159888500: system.cpu.stage4: Suspending [tid:0] due to cache miss. . 159888800: system.cpu.dcache_port: [tid:0]: [sn:41180]: [slot:4] Waking from cache access (vaddr.0x12009ed78, paddr:0x090d78) 159888800: system.cpu.dcache_port: [tid:0]: [sn:41180]: Processing cache access 159888800: system.cpu.dcache_port: [tid:0]: [sn:41180]: Bytes loaded were: 0000000000000000 159888800: system.cpu.dcache_port: [tid:0] Waking up from Cache Miss. 159888800: system.cpu: [tid:0]: Activating ... Note the Time differences. I would like to have my cache to have a latency of 2-3 cycles and not having the thread switched. Can it be done? Thanks, Yuval
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