Hi,

Thanks, it seems to work. I will do more tests just to be sure.

Nathanaël

Le 03/07/2012 20:25, Lena Olson a écrit :
Hi Nathanaël,

Oops, I didn't notice that case.  If you change the moveToTail to be
within the if blk->isValid() block above it, does that fix the problem
for you?

Lena

2012/7/3 Nathanaël Prémillieu <nprem...@irisa.fr>:
I am using SE mode. And this problem does not happen for all my simulations.
I have only five runs that have the problem. I also use more memory than the
default (2048MB instead of 512MB).
If you want, I can upload somewhere one of my checkpoint that have the
problem.
 From what I have seen (looking at the call stack), it seems that the
invalidateBlk function is called in the case where the current blk is the
'tempBlock'. I don't understand the whole code of the cache and memory
system, but it seems that this block is not really a block of the cache. So
trying to put it at the tail of some queue is maybe not possible.

Nathanaël

Le 02/07/2012 20:08, Ali Saidi a écrit :

I still haven't seen in happen. How long does it take for it to occur?
Can you make it happen during boot?

Thanks,

Ali

On 02.07.2012 05:17, Nathanaël Prémillieu wrote:

Hi,

It's the default configuration (--caches --l2cache) with the
arm_detailed cpu model.

Nathanaël



_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Reply via email to