incMissCount(pkt); check in cache_impl.hh On Wed, Jun 6, 2012 at 2:31 PM, Mahmood Naderan <mahmood...@gmail.com>wrote:
> Hi > I can not find where in the code, the demand misses are increased. I > expect that in cache_impl.hh::timingAccess() where an access is made > to the cache, this stat increments, But it doesn't! > > The stat look like: > demandMisses > .name(name() + ".demand_misses") > .desc("number of demand (read+write) misses") > .flags(total | nozero | nonan) > ; > demandMisses = SUM_DEMAND(misses); > for (int i = 0; i < system->maxMasters(); i++) { > demandMisses.subname(i, system->getMasterName(i)); > } > > However demandMisses is never increased. > > -- > // Naderan *Mahmood; > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- *thanks®ards * *BISWABANDAN*
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