So are TLB misses handled instantaneously in same tick? What about page faults? I would guess no page fault is raised in SE.
Thanks, Amin On Sat, Jun 2, 2012 at 11:58 AM, Gabe Black <[email protected]> wrote: > There *is* a TLB in SE mode, and address translation. The primary > difference is that in SE mode on misses it's filled from a magical page > table structure which the simulator maintains internally, and in FS mode > it uses the normal mechanism defined by the architecture. > > Gabe > > On 06/02/12 09:27, Ali Saidi wrote: > > There is no way to have one, "out-of-the-box." You'd need to do a fair > amount of work to build a page table and allocate memory in a > non-sequential way. Running in FS mode is probably the more expedient > method. > > > > Thanks, > > Ali > > > > > > > > On Jun 2, 2012, at 4:58 AM, Nathanaël Prémillieu wrote: > > > >> Ok, > >> Thanks for this answer. > >> Is there a way to way to had a tlb in SE mode, to have a more accurate > model ? > >> > >> Regards. > >> > >> Nathanaël > >> > >> Le 31/05/2012 18:00, Ali Saidi a écrit : > >>> Hi Nathanaël, > >>> > >>> In SE mode VA == PA so no translation is required. > >>> > >>> Thanks, > >>> Ali > >>> > >>> > >>> On 5/31/12 11:54 AM, "Nathanaël Prémillieu"<[email protected]> wrote: > >>> > >>>> Hi, > >>>> > >>>> I'm running gem5 in SE mode for the ARM architecture. I'm using the > >>>> 'arm_detailed' cpu type with --caches and --l2cache options activated. > >>>> However, all the statistics about the TLB (dtb and itb sections of the > >>>> statistics) are null: > >>>> system.cpu.dtb.inst_hits 0 # ITB inst hits > >>>> system.cpu.dtb.inst_misses 0 # ITB inst misses > >>>> system.cpu.dtb.read_hits 0 # DTB read hits > >>>> system.cpu.dtb.read_misses 0 # DTB read misses > >>>> ... > >>>> > >>>> (All the other stats seems to be ok) > >>>> > >>>> Is the tlb not activated by default? > >>>> Is there a problem in the statistics count? > >>>> > >>>> Regards. > >>>> > >>>> Nathanaël Prémillieu > >>>> _______________________________________________ > >>>> gem5-users mailing list > >>>> [email protected] > >>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > >>> > >>> -- IMPORTANT NOTICE: The contents of this email and any attachments > are confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > >>> > >>> _______________________________________________ > >>> gem5-users mailing list > >>> [email protected] > >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > >> _______________________________________________ > >> gem5-users mailing list > >> [email protected] > >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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