I just did this a few days ago.

Below is a snippet of my config script (you don't even need to recompile!)
 Not sure about the commented out forwarding paths. You might have been
getting assert failures if you didn't increase the forwardComSize
and backComSize, which are the size of the "buffers" holding the stages.

Assuming each system.cpu is a O3CPU, and you want a straight up linear
scaling of the default 5 stage pipeline. (where "depth" variable is really
depth multiplier)

for i in xrange(np):
    system.cpu[i].workload = multiprocesses[i]
     #main pipeline stages
    system.cpu[i].fetchToDecodeDelay  = depth
    system.cpu[i].decodeToRenameDelay = depth
    system.cpu[i].renameToIEWDelay    = 2*depth
    system.cpu[i].iewToCommitDelay    = depth

    #forwarding paths
    system.cpu[i].wbDepth              = depth
    system.cpu[i].commitToDecodeDelay  = depth
    #system.cpu[i].commitToFetchDelay  = depth
    #system.cpu[i].commitToIEWDelay    = depth
    #system.cpu[i].commitToRenameDelay = depth
    #system.cpu[i].decodeToFetchDelay  = depth
    #system.cpu[i].iewToDecodeDelay    = depth
    #system.cpu[i].iewToFetchDelay     = depth
    #system.cpu[i].iewToRenameDelay    = depth
    #system.cpu[i].issueToExecuteDelay = depth
    #system.cpu[i].renameToDecodeDelay = depth
    #system.cpu[i].renameToFetchDelay  = depth
    system.cpu[i].renameToROBDelay     = depth

    system.cpu[i].forwardComSize       = 5*depth
    system.cpu[i].backComSize          = 5*depth

    #width
    system.cpu[i].fetchWidth    = width
    system.cpu[i].decodeWidth   = width
    system.cpu[i].dispatchWidth = width
    system.cpu[i].issueWidth    = width
    system.cpu[i].wbWidth       = width
    system.cpu[i].renameWidth   = width
    system.cpu[i].commitWidth   = width
    system.cpu[i].squashWidth   = width

Good luck!


On Thu, Apr 12, 2012 at 1:06 PM, Ankita (Garg) Goel <gargank...@gmail.com>wrote:

> Hi,
>
> I want to model deeper pipeline in X86 simulation, around 20-31 stages.
> The ISCA tutorial slide mentioned that this could be achieved by adding
> varying amounts of delay in between the existing 7 stages in O3CPU.py.
> However, when I add some delays, the simulation aborts due to assert
> failure. Has anyone tried to do this ? Or anyone has any ideas on how this
> could be done ?
>
> Thanks a lot for your help !
>
> --
> Regards,
> Ankita
> Graduate Student
> Department of Computer Science
> University of Texas at Austin
>
>
>
> _______________________________________________
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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