thanks a lot On 3/30/12, biswabandan panda <[email protected]> wrote: > for i in xrange(options.num_cpus): > if options.caches: > if options.cpu_type == "arm_detailed": > icache = O3_ARM_v7a_ICache(size = options.l1i_size, > assoc = options.l1i_assoc, > block_size=options.cacheline_size) > dcache = O3_ARM_v7a_DCache(size = options.l1d_size, > assoc = options.l1d_assoc, > block_size=options.cacheline_size) > else: > icache = L1Cache(size = '32kB', > assoc = 1, > block_size=64) > icache.prefetcher = StridePrefetcher(degree = 3, latency = > '10ns', size = 30) > dcache = L1Cache(size = '32kB', > assoc = 2, > block_size=64) > dcache.prefetcher = StridePrefetcher(degree = 16, latency = > '10ns', size = 30) > > > On Fri, Mar 30, 2012 at 4:39 PM, Mahmood Naderan > <[email protected]>wrote: > >> Dear all, >> Since L2 cache is defined like >> system.l2 = L2Cache() >> >> the prefetcher is then attached like: >> system.l2.prefetcher = L2Prefetcher() >> >> where L2Prefetcher() is a class defined in Caches.py >> >> However the L1cache is defined differently within the cpu: >> cpu.addPrivateSplitL1Caches(L1Cache(), L1Cache()) >> >> Now how can I attach prefetcher to that? The prefetcher is part of >> cache however I don't know how can I access L1Cache after defining >> that within the cpu. >> >> Please let me know >> >> -- >> // Naderan *Mahmood; >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > > -- > > *thanks®ards > * > *BISWABANDAN* >
-- -- // Naderan *Mahmood; _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
