Another approach would be to have the needed information passed in explicitly as CPU parameters, e.g.,
cpu.cache_line_size_reg_value = xxx cpu.cache_assoc_reg_value = yyy and then leave it to the python config file to populate those correctly either by pulling params from the cache object or using the same option values as it's using to set up the cache. Steve On Thu, Mar 29, 2012 at 1:44 AM, Ali Saidi <[email protected]> wrote: > ** > > It would be nice, but I don't know of necessarily a better way to do this. > One possibility is adding pointers to the system object that can be > manually setup with the appropriate caches. > > For example > > system.l1d = system.l1dcache. > > Then the ARM system will have the pointers directly which should make it > easier to get the l1 and l2 caches as opposed to trying to weave around the > memory system. Anyone else have thoughts? > > > > Thanks, > > Ali > > > > > > On 29.03.2012 01:48, Anthony Gutierrez wrote: > > Hello, > I am working with some code that relies on the correct implementation of > the ARM CCSIDR ( > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/CIHGGJAB.html) > control > register see: src/arch/arm/isa.cc:readMiscReg(). I'm trying to implement > this (and the CSSELR > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/CIHGGJAB.html) > and was wondering what is the best way to obtain cache information from > this location. E.g., currently I'm doing something like for the icache: > BaseCPU *_cpu = tc->getCpuPtr(); > Cache*iCache = dynamic_cast*>( > _cpu->getPort("icache_port", 0)->getPeer()->getOwner()); > CCSIDR ccsidr = 0; > ccsidr.linSize = (log2(_cpu->getPort("icache_port", 0)->peerBlockSize() >> > 2)) - 2; > ccsidr.assoc = _cpu->getPort("icache_port", > 0)->getPeer()->getOwner()->getTags()->getAsso() - 1; > etc... > The get functions, getTags(), getAssoc() are my own. But, is there a more > general way to do this? I.e., without having to go through the cpu, > explicitly using LRU, etc.? > -- > Thanks, > Tony > > > > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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