It seems from your response that the L1 cache never receives any data. If
that's what you meant, I think you should read the code again. Secondly,
it is not necessary for the memory to directly reply to L1 cache, the L2
cache can respond to L1's request once it has got the response from the
memory.
--
Nilay
On Mon, 6 Feb 2012, Mahmood Naderan wrote:
I haven't found such algorithm in the code. Rather than that, I think
in the current code, the reply is made only to the last request. For
example, if L1D misses and then L2 misses, then memory reply only to
L2.
On 2/6/12, Nilay Vaish <[email protected]> wrote:
On Mon, 6 Feb 2012, Mahmood Naderan wrote:
Hi
while debugging, I observed this:
1- a HardPf address is issued (0xbc000) in dcache
2- it is checked in L2
3- L2 misses
4- The block is inserted in L2.
So I want to know, why it doesn't go back to dcache?
1254053000: system.cpu.dcache-pf: Requesting a hw_pf to issue
1254053000: system.cpu.dcache-pf: returning 0xbc000
1254053000: system.l2: ReadReq bc000 miss
1254094000: system.l2: replacement: replacing 124000 with bc000: clean
1254094000: system.l2: blk bc000 inserted to cache
Why is it necessary for the prefetched data to be brought in to dcache?
May be the code has been written so that the data gets prefetched in to
the L2 cache.
--
Nilay
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--
// Naderan *Mahmood;
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