yes. The degree is 4. One more question is that what is the *unit* of degree?
Does it mean 4 blocks? or it means 4 memory address?

On 2/4/12, biswabandan panda <[email protected]> wrote:
> What's the degree of the prefetcher? I have found out the number like this
> for degree-4
>
> On Sat, Feb 4, 2012 at 12:30 PM, Mahmood Naderan
> <[email protected]>wrote:
>
>> hi
>> While simulating a workload using X86_SE, I noticed that L2 misses are
>> large but prefetch issue rate is very very small.
>>
>> system.l2.prefetcher.num_hwpf_identified
>> 220                                 # number of hwpf identified
>> system.l2.prefetcher.num_hwpf_already_in_mshr
>> 0                                 # number of hwpf that were already
>> in mshr
>> system.l2.prefetcher.num_hwpf_already_in_cache
>> 17                                 # number of hwpf that were already
>> in the cache
>> system.l2.prefetcher.num_hwpf_already_in_prefetcher
>> 0                                 # number of hwpf that were already
>> in the prefetch queue
>> system.l2.prefetcher.num_hwpf_evicted
>> 0                                 # number of hwpf removed due to no
>> buffer left
>> system.l2.prefetcher.num_hwpf_removed_MSHR_hit
>> 0                                 # number of hwpf removed because
>> MSHR allocated
>> system.l2.prefetcher.num_hwpf_issued
>> 203                                 # number of hwpf issued
>> system.l2.prefetcher.num_hwpf_span_page
>> 0                                 # number of hwpf spanning a virtual
>> page
>> system.l2.prefetcher.num_hwpf_squashed_from_miss
>> 0                                 # number of hwpf that got squashed
>> due to a miss aborting calculation time
>>
>> system.l2.ReadReq_hits
>> 7628303                                 # number of ReadReq hits
>> system.l2.Writeback_hits
>> 138429                                 # number of Writeback hits
>> system.l2.ReadExReq_hits
>> 17957                                 # number of ReadExReq hits
>> system.l2.demand_hits
>> 7646260                                 # number of demand
>> (read+write) hits
>> system.l2.overall_hits
>> 7646260                                 # number of overall hits
>> system.l2.ReadReq_misses
>> 21786661                                 # number of ReadReq misses
>> system.l2.ReadExReq_misses
>> 27500                                 # number of ReadExReq misses
>> system.l2.demand_misses
>> 21814161                                 # number of demand
>> (read+write) misses
>> system.l2.overall_misses
>> 21814161                                 # number of overall misses
>>
>>
>>
>> As you can see number of misses are much larger than hits, but number
>> of prefetches are very very small.
>>
>> Is there any suggestion about that?
>> Thanks
>> --
>> // Naderan *Mahmood;
>> _______________________________________________
>> gem5-users mailing list
>> [email protected]
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>
>
>
> --
>
> *thanks&regards
> *
> *BISWABANDAN*
>


-- 
--
// Naderan *Mahmood;
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Reply via email to