Thanks.  Actually I only tested it on ARM_SE and ARM_FS.  Let me know if it
also works for other processors.

 

In addition, I actually made more modification on the DRAMsim2 side.  Maybe
the most important one is that I changed the way how DRAMsim2 reports
latency/bandwidth statistics. DRAMsim2 reports all the statistics after
every EPOCH, and then resets all the numbers.  For Gem5 users who are only
interested in the statistics over the entire simulation time, you might want
to change the codes in DRAMsim2/MemoryController.cpp and make similar
changes like what I've done (that's NOT in the patch since it's more
DRAMsim2-related).

 

Best,

Xiangyu

 

From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Andrew Cebulski
Sent: Sunday, December 18, 2011 6:38 AM
To: gem5-users@gem5.org
Subject: Re: [gem5-users] A Patch for DRAMsim2 Integration

 

Thanks for the integration patch Xiangyu!  I'll let you know if I come
across any bugs.

 

-Andrew

 

 

Date: Sun, 18 Dec 2011 01:48:58 -0800
From: "Dong, Xiangyu" <riosher...@gmail.com>
To: "gem5 users mailing list" <gem5-users@gem5.org>
Subject: [gem5-users] A Patch for DRAMsim2 Integration
Message-ID: <001201ccbd6a$45102210$cf306630$@gmail.com>
Content-Type: text/plain; charset="us-ascii"

Hi all,



I have a Gem5+DRAMsim2 patch.  I've tested it under both SE and FS modes.
I'm willing to share it here.



For those who have such needs, please go to my website
www.cse.psu.edu/~xydong to download the patch and test it.  To enable
DRAMSim2, use se_dramsim2.py script instead of se.py (for FS, you can create
by yourself).  The basic idea to enable the DRAMsim2 module is to use the
derived DRAMMemory class instead of PhysicalMemory class.



Please let me know if there are bugs.



Thank you!



Best,

Xiangyu Dong

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