For double check:
>it dequeues a prefetch request from the prefetch queue
PacketPtr pkt = prefetcher->getPacket();
>into miss_mshr
return allocateMissBuffer(pkt, curTick(), false);
>and generate the bus request for that prefetch request subsequently
PacketPtr snoop_pkt = new Packet(tgt_pkt, true);
snoop_pkt->setExpressSnoop();
snoop_pkt->senderState = mshr;
cpuSidePort->sendTiming(snoop_pkt);
>But everytime mshr will keep track of all in-flight request,
>irrespective of it is demand request/prefetch request sent to the bus.
if (mshr) {
...
} else {
....
allocateMissBuffer(pkt, time, true);
}
If i understand correctly, when a read miss occurs, an entry is
allocated in pf queue and an MSHR entry is allocated so miss_mshr has
one element. Now in getNextMSHR(), we check. Since miss_mshr size is
non zero, the entry is poped and get serviced. In another iteration,
the miss_msr is zero but pf queue has an element (last miss). So it is
poped from pf queue and get serviced.
Right?
On 12/17/11, Dibakar Gope <[email protected]> wrote:
> Hi, that is something as follows:
>
> basically it prioritizes the demand misses and writeback requests in the
> miss-mshr and write-mshr respectively first...but whenever it finds both the
> queues as empty, it dequeues a prefetch request from the prefetch queue into
> miss_mshr and generate the bus request for that prefetch request
> subsequently. But everytime mshr will keep track of all in-flight request,
> irrespective of it is demand request/prefetch request sent to the bus.
> Prefetch-on-miss parameter is somewhat orthogonal to it, it basically drives
> the core to queue a prefetch request to the prefetch queue only in case of a
> demand miss.
>
> On 12/17/11, Mahmood Naderan wrote:
>> Hi,
>> Yesterday, I asked a question about prefetch on miss. However have not
>> get any answer yet. As you also questioned and andswered about gem5
>> prefetcher, we can mesh our minds to see what does gem5 actually do.
>>
>> The simulator says it can prefetch on misses. However based on an
>> assertion line
>>
>> assert(!miss_mshr && !write_mshr);
>>
>> prefetching only is done when there is no entry in miss mshr and write
>> mshr.
>> As the mshr tracks misses, it is a strange line. Do you have any comment?
>>
>> thanks
>> --
>> // Naderan *Mahmood;
>
>
--
--
// Naderan *Mahmood;
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