When I debug O3CPUAll, there is only received timing. It is unknown when the packet had been sent.
**** REAL SIMULATION **** info: Entering event queue @ 1254044000. Starting simulation... 1254044000: system.switch_cpus: FullO3CPU: Ticking main, FullO3CPU. 1254044000: system.switch_cpus.fetch: Running stage. 1254044000: system.switch_cpus.fetch: Attempting to fetch from [tid:0] 1254044000: system.switch_cpus.fetch: [tid:0]: Attempting to translate and read instruction, starting at PC (0x405bdd=>0x405be5).(0=>1). 1254044000: system.switch_cpus.fetch: [tid:0] Fetching cache line 0x405bc0 for addr 0x405bd8 1254044000: system.switch_cpus: CPU already running. 1254044000: system.switch_cpus.fetch: Fetch: Doing instruction read. 1254044000: system.switch_cpus.fetch: [tid:0]: Doing Icache access. 1254044000: system.switch_cpus.fetch: [tid:0]: Activity: Waiting on I-cache response. 1254044000: system.switch_cpus.decode: Processing [tid:0] 1254044000: system.switch_cpus.decode: [tid:0]: Not blocked, so attempting to run stage. 1254044000: system.switch_cpus.decode: [tid:0] Nothing to do, breaking out early. 1254044000: system.switch_cpus.rename: Processing [tid:0] 1254044000: system.switch_cpus.rename: [tid:0]: Free IQ: 64, Free ROB: 192, Free LSQ: 32 1254044000: system.switch_cpus.rename: [tid:0]: 0 instructions not yet in ROB 1254044000: system.switch_cpus.rename: [tid:0]: Not blocked, so attempting to run stage. 1254044000: system.switch_cpus.rename: [tid:0]: Nothing to do, breaking out early. 1254044000: system.switch_cpus.iew: Issue: Processing [tid:0] 1254044000: system.switch_cpus.iew: [tid:0] Not blocked, so attempting to run dispatch. 1254044000: system.switch_cpus.iq: Attempting to schedule ready instructions from the IQ. 1254044000: system.switch_cpus.iq: Not able to schedule any instructions. 1254044000: system.switch_cpus.iew: Processing [tid:0] 1254044000: system.switch_cpus.iew: [tid:0], Dispatch dispatched 0 instructions. 1254044000: system.switch_cpus.iew: IQ has 64 free entries (Can schedule: 0). LSQ has 32 free entries. 1254044000: system.switch_cpus.iew: IEW switching to idle 1254044000: system.switch_cpus.iew: Deactivating stage. 1254044000: system.switch_cpus: Activity: 1 1254044000: system.switch_cpus.iew: Activity this cycle. 1254044000: system.switch_cpus.commit: Getting instructions from Rename stage. 1254044000: system.switch_cpus.commit: Trying to commit instructions in the ROB. 1254044000: system.switch_cpus.commit: [tid:0]: ROB has 0 insts & 192 free entries. 1254044000: system.switch_cpus.commit: Deactivating stage. 1254044000: system.switch_cpus: Stage 4 already inactive. 1254044000: system.switch_cpus: Scheduling next tick! 1254045000: system.switch_cpus.fetch-iport: Received timing 1254045000: system.switch_cpus.fetch: [tid:0] Waking up from cache miss. On 12/6/11, Mahmood Naderan <[email protected]> wrote: > lsq_unit.hh has > > if (!dcachePort->sendTiming(data_pkt)) { > > but the definition doesn't mention which side. > > > On 12/6/11, Dibakar Gope <[email protected]> wrote: >> Hi, I guess, lsq_unit.hh, lsq_unit_impl.hh (src/cpu/o3) should have that >> sendTiming function. >> >> On 12/06/11, Mahmood Naderan wrote: >>> Hi, >>> in cache_impl.hh, there is a function: >>> >>> bool Cache<TagStore>::CpuSidePort::recvTiming(PacketPtr pkt) >>> >>> I expect that a corresponding function exists in cpu side (fetch, ...) >>> that looks like >>> >>> CacheSidePort::sendTiming(PacketPtr pkt) >>> >>> however I couldn't find such thing. If there exists one with different >>> name please let me know. >>> How can I send a pkt from cpu to cache. Any example? >>> >>> -- >>> // Naderan *Mahmood; >>> _______________________________________________ >>> gem5-users mailing list >>> [email protected] >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > -- > -- > // Naderan *Mahmood; > -- -- // Naderan *Mahmood; _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
