Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71138?usp=email )
Change subject: dev-arm: Treat GICv3 reserved addresses as RES0
......................................................................
dev-arm: Treat GICv3 reserved addresses as RES0
According to the GIC specification (IHI0069) reserved addresses in the
GIC memory map are treated as RES0. We allow to disable this behaviour
and panic instead (reserved_res0 = False, which is what we have been
doing so far) to catch development bugs (in gem5 and in the guest SW)
Change-Id: I23f98519c2f256c092a52425735b8792bae7a2c7
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/dev/arm/Gic.py
M src/dev/arm/gic_v3.hh
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_redistributor.cc
4 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index 41d602b..02df33f 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -315,6 +315,15 @@
gicv4 = Param.Bool(False, "GIC is GICv4 compatible")
+ reserved_res0 = Param.Bool(
+ True,
+ "According to the GIC specification (IHI0069) "
+ "reserved addresses in the GIC memory map are treated as RES0. "
+ "We allow to disable this behaviour and panic instead "
+ "(reserved_res0 = False) to catch development bugs "
+ "(in gem5 and in the guest SW)",
+ )
+
def interruptCells(self, int_type, int_num, int_trigger,
partition=None):
"""
Interupt cells generation helper:
diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh
index 2ea6a98..80c5afd 100644
--- a/src/dev/arm/gic_v3.hh
+++ b/src/dev/arm/gic_v3.hh
@@ -167,6 +167,17 @@
Tick write(PacketPtr pkt) override;
bool supportsVersion(GicVersion version) override;
+ template<typename... Args>
+ void
+ reserved(const char* fmt, Args... args) const
+ {
+ if (params().reserved_res0) {
+ warn(fmt, args...);
+ } else {
+ panic(fmt, args...);
+ }
+ }
+
public:
Gicv3(const Params &p);
diff --git a/src/dev/arm/gic_v3_distributor.cc
b/src/dev/arm/gic_v3_distributor.cc
index 1cb485c..af30692 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -505,8 +505,8 @@
return 0; // RES0
default:
- panic("Gicv3Distributor::read(): invalid offset %#x\n", addr);
- break;
+ gic->reserved("Gicv3Distributor::read(): invalid offset %#x\n",
addr);
+ return 0; // RES0
}
}
@@ -999,7 +999,7 @@
}
default:
- panic("Gicv3Distributor::write(): invalid offset %#x\n", addr);
+ gic->reserved("Gicv3Distributor::write(): invalid offset %#x\n",
addr);
break;
}
}
diff --git a/src/dev/arm/gic_v3_redistributor.cc
b/src/dev/arm/gic_v3_redistributor.cc
index e4380ef..67d6e42 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -377,8 +377,8 @@
return 0;
default:
- panic("Gicv3Redistributor::read(): invalid offset %#x\n", addr);
- break;
+ gic->reserved("Gicv3Redistributor::read(): invalid offset %#x\n",
addr);
+ return 0; // RES0
}
}
@@ -704,7 +704,7 @@
}
default:
- panic("Gicv3Redistributor::write(): invalid offset %#x\n", addr);
+ gic->reserved("Gicv3Redistributor::write(): invalid offset %#x\n",
addr);
break;
}
}
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I23f98519c2f256c092a52425735b8792bae7a2c7
Gerrit-Change-Number: 71138
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
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