Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70637?usp=email )
Change subject: arch-arm: Fix position of AA64ISAR0.AES bitfield
......................................................................
arch-arm: Fix position of AA64ISAR0.AES bitfield
The bitfield was wrongly [1] placed in the LSBs of the register
[1]: https://developer.arm.com/documentation/ddi0601/2022-03/\
AArch64-Registers/\
ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0
Change-Id: I577a79e16931a0e1334a9b24459553e2899341f0
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70637
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved
Richard Cooper: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/regs/misc_types.hh
b/src/arch/arm/regs/misc_types.hh
index e446ce5..e6f7e40 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -123,7 +123,7 @@
Bitfield<19, 16> crc32;
Bitfield<15, 12> sha2;
Bitfield<11, 8> sha1;
- Bitfield<3, 0> aes;
+ Bitfield<7, 4> aes;
EndBitUnion(AA64ISAR0)
BitUnion64(AA64ISAR1)
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I577a79e16931a0e1334a9b24459553e2899341f0
Gerrit-Change-Number: 70637
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
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