Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70598?usp=email )
Change subject: arch-riscv: Add BS format isa
......................................................................
arch-riscv: Add BS format isa
This format is helper for aes32dsi, aes32dsmi, aes32esi, aes32esmi,
sm4ed, sm4ks disassembly
Change-Id: Ieff1932e267efc0a8c5fd8e557fc467dc376da4e
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/bs.cc
A src/arch/riscv/insts/bs.hh
M src/arch/riscv/isa/decoder.isa
A src/arch/riscv/isa/formats/bs.isa
M src/arch/riscv/isa/formats/formats.isa
M src/arch/riscv/isa/includes.isa
7 files changed, 173 insertions(+), 12 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index 80592a3..704152c 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -28,6 +28,7 @@
Import('*')
Source('amo.cc', tags='riscv isa')
+Source('bs.cc', tags='riscv isa')
Source('compressed.cc', tags='riscv isa')
Source('mem.cc', tags='riscv isa')
Source('standard.cc', tags='riscv isa')
diff --git a/src/arch/riscv/insts/bs.cc b/src/arch/riscv/insts/bs.cc
new file mode 100644
index 0000000..7a9e6e7
--- /dev/null
+++ b/src/arch/riscv/insts/bs.cc
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2023 Google LLC
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/riscv/insts/bs.hh"
+
+#include <sstream>
+#include <string>
+
+#include "arch/riscv/utility.hh"
+
+namespace gem5
+{
+
+namespace RiscvISA
+{
+
+std::string
+BSOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
+ registerName(srcRegIdx(0)) << ", " << registerName(srcRegIdx(1)) <<
+ ", " << (uint32_t)bs;
+ return ss.str();
+}
+
+} // namespace RiscvISA
+} // namespace gem5
diff --git a/src/arch/riscv/insts/bs.hh b/src/arch/riscv/insts/bs.hh
new file mode 100644
index 0000000..7a063fb
--- /dev/null
+++ b/src/arch/riscv/insts/bs.hh
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Google LLC
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_RISCV_BS_INST_HH__
+#define __ARCH_RISCV_BS_INST_HH__
+
+#include "arch/riscv/insts/static_inst.hh"
+
+namespace gem5
+{
+
+namespace RiscvISA
+{
+
+class BSOp : public RiscvStaticInst
+{
+ protected:
+ uint8_t bs;
+
+ BSOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass), bs(0)
+ {}
+
+ std::string generateDisassembly(
+ Addr pc, const loader::SymbolTable *symtab) const override;
+};
+
+} // namespace RiscvISA
+} // namespace gem5
+
+#endif // __ARCH_RISCV_BS_INST_HH__
+
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index c9c815f..9c0cf45 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1021,27 +1021,27 @@
}
}
0x11: decode RVTYPE {
- 0x0: aes32esi({{
- Rd_sw = _rvk_emu_aes32esi(Rs1_sw, Rs2_sw,
(uint8_t)BS);
+ 0x0: BSOp::aes32esi({{
+ Rd_sw = _rvk_emu_aes32esi(Rs1_sw, Rs2_sw, bs);
}});
}
0x13: decode RVTYPE {
- 0x0: aes32esmi({{
- Rd_sw = _rvk_emu_aes32esmi(Rs1_sw, Rs2_sw,
(uint8_t)BS);
+ 0x0: BSOp::aes32esmi({{
+ Rd_sw = _rvk_emu_aes32esmi(Rs1_sw, Rs2_sw, bs);
}});
}
0x15: decode RVTYPE {
- 0x0: aes32dsi({{
- Rd_sw = _rvk_emu_aes32dsi(Rs1_sw, Rs2_sw,
(uint8_t)BS);
+ 0x0: BSOp::aes32dsi({{
+ Rd_sw = _rvk_emu_aes32dsi(Rs1_sw, Rs2_sw, bs);
}});
}
0x17: decode RVTYPE {
- 0x0: aes32dsmi({{
- Rd_sw = _rvk_emu_aes32dsmi(Rs1_sw, Rs2_sw,
(uint8_t)BS);
+ 0x0: BSOp::aes32dsmi({{
+ Rd_sw = _rvk_emu_aes32dsmi(Rs1_sw, Rs2_sw, bs);
}});
}
- 0x18: sm4ed({{
- Rd_sw = _rvk_emu_sm4ed(Rs1_sw, Rs2_sw,
(uint8_t)BS);
+ 0x18: BSOp::sm4ed({{
+ Rd_sw = _rvk_emu_sm4ed(Rs1_sw, Rs2_sw, bs);
}});
0x19: decode BS {
0x0: decode RVTYPE {
@@ -1050,8 +1050,8 @@
}});
}
}
- 0x1a: sm4ks({{
- Rd_sw = _rvk_emu_sm4ks(Rs1_sw, Rs2_sw,
(uint8_t)BS);
+ 0x1a: BSOp::sm4ks({{
+ Rd_sw = _rvk_emu_sm4ks(Rs1_sw, Rs2_sw, bs);
}});
0x1b: decode BS {
0x0: decode RVTYPE {
diff --git a/src/arch/riscv/isa/formats/bs.isa
b/src/arch/riscv/isa/formats/bs.isa
new file mode 100644
index 0000000..d413502
--- /dev/null
+++ b/src/arch/riscv/isa/formats/bs.isa
@@ -0,0 +1,48 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2023 Google LLC
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+// Declaration templates.
+
+def template BSConstructor {{
+ %(class_name)s::%(class_name)s(ExtMachInst machInst)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+ {
+ %(set_reg_idx_arr)s;
+ %(constructor)s;
+ %(bs_code)s;
+ }
+}};
+
+def format BSOp(code, bs_code='bs = (uint8_t)BS;', *opt_flags) {{
+ iop = InstObjParams(name, Name, 'BSOp',
+ {'bs_code': bs_code, 'code': code}, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BSConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
diff --git a/src/arch/riscv/isa/formats/formats.isa
b/src/arch/riscv/isa/formats/formats.isa
index 2a6b910..1974943 100644
--- a/src/arch/riscv/isa/formats/formats.isa
+++ b/src/arch/riscv/isa/formats/formats.isa
@@ -36,6 +36,7 @@
##include "mem.isa"
##include "fp.isa"
##include "amo.isa"
+##include "bs.isa"
// Include formats for nonstandard extensions
##include "compressed.isa"
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index a5cc5e8..8dddc2f 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -46,6 +46,7 @@
#include <specialize.h>
#include "arch/riscv/insts/amo.hh"
+#include "arch/riscv/insts/bs.hh"
#include "arch/riscv/insts/compressed.hh"
#include "arch/riscv/insts/mem.hh"
#include "arch/riscv/insts/pseudo.hh"
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ieff1932e267efc0a8c5fd8e557fc467dc376da4e
Gerrit-Change-Number: 70598
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
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