Roger Chang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70357?usp=email )
Change subject: arch-riscv: Treat RVC HINT as nops rather than trap
......................................................................
arch-riscv: Treat RVC HINT as nops rather than trap
The RVC HINT can be implemented as no-op to ignore them. See the
section 18.7 of RISC-V spec Volume I for more details
Change-Id: I88a62fd5722ac542ecfef5fcb80fef2ce04f010f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70357
Tested-by: kokoro <noreply+kok...@google.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 10 insertions(+), 27 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 69b3055..d89a0c9 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -152,11 +152,9 @@
}}, {{
if ((RC1 == 0) != (imm == 0)) {
if (RC1 == 0) {
- return std::make_shared<IllegalInstFault>(
- "source reg x0", machInst);
- } else { // imm == 0
- return std::make_shared<IllegalInstFault>(
- "immediate = 0", machInst);
+ // imm != 0 is HINT
+ } else {
+ // imm == 0 is HINT
}
}
Rc1_sd = rvSext(Rc1_sd + imm);
@@ -179,10 +177,7 @@
0x2: CIOp::c_li({{
imm = sext<6>(CIMM5 | (CIMM1 << 5));
}}, {{
- if (RC1 == 0) {
- return std::make_shared<IllegalInstFault>(
- "source reg x0", machInst);
- }
+ // RC1 == 0 is HINT
Rc1_sd = imm;
}});
0x3: decode RC1 {
@@ -202,10 +197,7 @@
default: CIOp::c_lui({{
imm = sext<6>(CIMM5 | (CIMM1 << 5)) << 12;
}}, {{
- if (RC1 == 0 || RC1 == 2) {
- return std::make_shared<IllegalInstFault>(
- "source reg x0", machInst);
- }
+ // RC1 == 0 is HINT
if (imm == 0) {
return std::make_shared<IllegalInstFault>(
"immediate = 0", machInst);
@@ -223,8 +215,7 @@
"shmat[5] != 0", machInst);
}
if (imm == 0) {
- return std::make_shared<IllegalInstFault>(
- "immediate = 0", machInst);
+ // C.SRLI64, HINT for RV32/RV64
}
// The MSB can never be 1, hence no need to sign ext.
Rp1 = rvZext(Rp1) >> imm;
@@ -237,8 +228,7 @@
"shmat[5] != 0", machInst);
}
if (imm == 0) {
- return std::make_shared<IllegalInstFault>(
- "immediate = 0", machInst);
+ // C.SRAI64, HINT for RV32/RV64
}
Rp1_sd = rvSext(Rp1_sd) >> imm;
}}, uint64_t);
@@ -306,13 +296,9 @@
"shmat[5] != 0", machInst);
}
if (imm == 0) {
- return std::make_shared<IllegalInstFault>(
- "immediate = 0", machInst);
+ // C.SLLI64, HINT for RV32/RV64
}
- if (RC1 == 0) {
- return std::make_shared<IllegalInstFault>(
- "source reg x0", machInst);
- }
+ // RC1 == 0 is HINT
Rc1 = rvSext(Rc1 << imm);
}}, uint64_t);
format CompressedLoad {
@@ -375,10 +361,7 @@
NPC = rvZext(Rc1);
}}, IsIndirectControl, IsUncondControl);
default: CROp::c_mv({{
- if (RC1 == 0) {
- return std::make_shared<IllegalInstFault>(
- "source reg x0", machInst);
- }
+ // RC1 == 0 is HINT
Rc1 = rvSext(Rc2);
}});
}
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I88a62fd5722ac542ecfef5fcb80fef2ce04f010f
Gerrit-Change-Number: 70357
Gerrit-PatchSet: 5
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Hoa Nguyen <hoangu...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Roger Chang <rogerycch...@google.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Yu-hsin Wang <yuhsi...@google.com>
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