Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70469?usp=email )
Change subject: arch-arm: Remove ISA::initID64
......................................................................
arch-arm: Remove ISA::initID64
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Change-Id: I3d03ee15df46fa7d9a9ec439b26e99baf33cbb5e
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70469
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/regs/misc.cc
3 files changed, 123 insertions(+), 125 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b1e463a..d87e9c5 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -142,12 +142,6 @@
miscRegs[idx] = lookUpMiscReg[idx].reset();
}
- // We always initialize AArch64 ID registers even
- // if we are in AArch32. This is done since if we
- // are in SE mode we don't know if our ArmProcess is
- // AArch32 or AArch64
- initID64(p);
-
if (FullSystem && system->highestELIs64()) {
// Initialize AArch64 state
clear64(p);
@@ -256,124 +250,6 @@
}
void
-ISA::initID64(const ArmISAParams &p)
-{
- // Initialize configurable id registers
- miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1;
- miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1;
-
- AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1;
- dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3
- miscRegs[MISCREG_ID_AA64DFR0_EL1] = dfr0_el1;
-
- miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1;
-
- // SVE
- miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0
- if (release->has(ArmExtension::SECURITY)) {
- miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
- } else if (release->has(ArmExtension::VIRTUALIZATION)) {
- miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
- } else {
- miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
- }
-
- // SME
-
- // Set up the SME SMIDR
- // [63:32] RES0
- // [31:24] Implementer - default this to Arm Limited
- // [23:16] SMCU Revision - set to 0 as we don't model an SMCU
- // [15] SMPS - We don't do priorities in gem5, so disable
- // [14:12] RES0
- // [11:0] Affinity - we implement per-CPU SME, so set to 0 (no SMCU)
- SMIDR smidr_el1 = 0;
- smidr_el1.affinity = 0;
- smidr_el1.smps = 0;
- smidr_el1.implementer = 0x41;
- miscRegs[MISCREG_SMIDR_EL1] = smidr_el1;
-
- AA64SMFR0 smfr0_el1 = 0;
- smfr0_el1.f32f32 = 0x1;
- // The following BF16F32 is actually not implemented due to a lack
- // of BF16 support in gem5's fplib. However, as per the SME spec the
- // _only_ allowed value is 0x1.
- smfr0_el1.b16f32 = 0x1;
- smfr0_el1.f16f32 = 0x1;
- smfr0_el1.i8i32 = 0xF;
- smfr0_el1.f64f64 = 0x1;
- smfr0_el1.i16i64 = 0xF;
- smfr0_el1.smEver = 0;
- smfr0_el1.fa64 = 0x1;
- miscRegs[MISCREG_ID_AA64SMFR0_EL1] = smfr0_el1;
-
- // We want to support FEAT_SME_FA64. Therefore, we enable it in all
- // SMCR_ELx registers by default. Runtime software might change this
- // later, but given that gem5 doesn't disable instructions based on
- // this flag we default to the most representative value.
- miscRegs[MISCREG_SMCR_EL3] = 0x1 << 31;
- miscRegs[MISCREG_SMCR_EL2] = 0x1 << 31;
- miscRegs[MISCREG_SMCR_EL1] = 0x1 << 31;
-
- // Set the vector default vector length
- if (release->has(ArmExtension::SECURITY)) {
- miscRegs[MISCREG_SMCR_EL3] |= ((smeVL - 1) & 0xF);
- } else if (release->has(ArmExtension::VIRTUALIZATION)) {
- miscRegs[MISCREG_SMCR_EL2] |= ((smeVL - 1) & 0xF);
- } else {
- miscRegs[MISCREG_SMCR_EL1] |= ((smeVL - 1) & 0xF);
- }
-
- AA64PFR0 pfr0_el1 = 0;
- pfr0_el1.el3 = release->has(ArmExtension::SECURITY) ? 0x2 : 0x0;
- pfr0_el1.el2 = release->has(ArmExtension::VIRTUALIZATION) ? 0x2 : 0x0;
- pfr0_el1.sve = release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0;
- pfr0_el1.sel2 = release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0;
- miscRegs[MISCREG_ID_AA64PFR0_EL1] = pfr0_el1;
-
- AA64MMFR0 mmfr0_el1 = p.id_aa64mmfr0_el1;
- mmfr0_el1.asidbits = haveLargeAsid64 ? 0x2 : 0x0;
- mmfr0_el1.parange = encodePhysAddrRange64(physAddrRange);
- miscRegs[MISCREG_ID_AA64MMFR0_EL1] = mmfr0_el1;
-
- AA64ISAR0 isar0_el1 = p.id_aa64isar0_el1;
- if (release->has(ArmExtension::CRYPTO)) {
- isar0_el1.crc32 = 1;
- isar0_el1.sha2 = 1;
- isar0_el1.sha1 = 1;
- isar0_el1.aes = 2;
- } else {
- isar0_el1.crc32 = 0;
- isar0_el1.sha2 = 0;
- isar0_el1.sha1 = 0;
- isar0_el1.aes = 0;
- }
- isar0_el1.atomic = release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0;
- isar0_el1.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
- isar0_el1.tme = release->has(ArmExtension::TME) ? 0x1 : 0x0;
- miscRegs[MISCREG_ID_AA64ISAR0_EL1] = isar0_el1;
-
- AA64ISAR1 isar1_el1 = p.id_aa64isar1_el1;
- isar1_el1.apa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0;
- isar1_el1.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0;
- isar1_el1.fcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0;
- isar1_el1.gpa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0;
- miscRegs[MISCREG_ID_AA64ISAR1_EL1] = isar1_el1;
-
- AA64MMFR1 mmfr1_el1 = p.id_aa64mmfr1_el1;
- mmfr1_el1.vmidbits = release->has(ArmExtension::FEAT_VMID16) ? 0x2 :
0x0;
- mmfr1_el1.vh = release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0;
- mmfr1_el1.hpds = release->has(ArmExtension::FEAT_HPDS) ? 0x1 : 0x0;
- mmfr1_el1.pan = release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0;
- miscRegs[MISCREG_ID_AA64MMFR1_EL1] = mmfr1_el1;
-
- AA64MMFR2 mmfr2_el1 = p.id_aa64mmfr2_el1;
- mmfr2_el1.uao = release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0;
- mmfr2_el1.varange = release->has(ArmExtension::FEAT_LVA) ? 0x1 : 0x0;
- miscRegs[MISCREG_ID_AA64MMFR2_EL1] = mmfr2_el1;
-}
-
-void
ISA::startup()
{
BaseISA::startup();
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 8419641..55fbd03 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -172,7 +172,6 @@
protected:
void clear32(const ArmISAParams &p);
void clear64(const ArmISAParams &p);
- void initID64(const ArmISAParams &p);
void addressTranslation(MMU::ArmTranslationType tran_type,
BaseMMU::Mode mode, Request::Flags flags, RegVal val);
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 7cff4ca..ef5d741 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3692,36 +3692,101 @@
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64PFR0_EL1)
+ .reset([this,release=release,tc=tc](){
+ AA64PFR0 pfr0_el1 = 0;
+ pfr0_el1.el0 = 0x2;
+ pfr0_el1.el1 = 0x2;
+ pfr0_el1.el2 = release->has(ArmExtension::VIRTUALIZATION) ?
0x2 : 0x0;
+ pfr0_el1.el3 = release->has(ArmExtension::SECURITY) ? 0x2 : 0x0;
+ pfr0_el1.sve = release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0;
+ pfr0_el1.sel2 = release->has(ArmExtension::FEAT_SEL2) ? 0x1 :
0x0;
+ pfr0_el1.gic = FullSystem && getGICv3CPUInterface(tc) ? 0x1 : 0;
+ return pfr0_el1;
+ }())
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64PFR1_EL1)
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64DFR0_EL1)
+ .reset([p](){
+ AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1;
+ dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3
+ return dfr0_el1;
+ }())
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64DFR1_EL1)
+ .reset(p.id_aa64dfr1_el1)
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64AFR0_EL1)
+ .reset(p.id_aa64afr0_el1)
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64AFR1_EL1)
+ .reset(p.id_aa64afr1_el1)
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64ISAR0_EL1)
+ .reset([p,release=release](){
+ AA64ISAR0 isar0_el1 = p.id_aa64isar0_el1;
+ if (release->has(ArmExtension::CRYPTO)) {
+ isar0_el1.crc32 = 1;
+ isar0_el1.sha2 = 1;
+ isar0_el1.sha1 = 1;
+ isar0_el1.aes = 2;
+ } else {
+ isar0_el1.crc32 = 0;
+ isar0_el1.sha2 = 0;
+ isar0_el1.sha1 = 0;
+ isar0_el1.aes = 0;
+ }
+ isar0_el1.atomic = release->has(ArmExtension::FEAT_LSE) ? 0x2 :
0x0;
+ isar0_el1.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
+ isar0_el1.tme = release->has(ArmExtension::TME) ? 0x1 : 0x0;
+ return isar0_el1;
+ }())
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64ISAR1_EL1)
+ .reset([p,release=release](){
+ AA64ISAR1 isar1_el1 = p.id_aa64isar1_el1;
+ isar1_el1.apa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 :
0x0;
+ isar1_el1.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 :
0x0;
+ isar1_el1.fcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 :
0x0;
+ isar1_el1.gpa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 :
0x0;
+ return isar1_el1;
+ }())
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64MMFR0_EL1)
+ .reset([p,asidbits=haveLargeAsid64,parange=physAddrRange](){
+ AA64MMFR0 mmfr0_el1 = p.id_aa64mmfr0_el1;
+ mmfr0_el1.asidbits = asidbits ? 0x2 : 0x0;
+ mmfr0_el1.parange = encodePhysAddrRange64(parange);
+ return mmfr0_el1;
+ }())
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64MMFR1_EL1)
+ .reset([p,release=release](){
+ AA64MMFR1 mmfr1_el1 = p.id_aa64mmfr1_el1;
+ mmfr1_el1.vmidbits = release->has(ArmExtension::FEAT_VMID16) ?
0x2 : 0x0;
+ mmfr1_el1.vh = release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0;
+ mmfr1_el1.hpds = release->has(ArmExtension::FEAT_HPDS) ? 0x1 :
0x0;
+ mmfr1_el1.pan = release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0;
+ return mmfr1_el1;
+ }())
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64MMFR2_EL1)
+ .reset([p,release=release](){
+ AA64MMFR2 mmfr2_el1 = p.id_aa64mmfr2_el1;
+ mmfr2_el1.uao = release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0;
+ mmfr2_el1.varange = release->has(ArmExtension::FEAT_LVA) ? 0x1 :
0x0;
+ return mmfr2_el1;
+ }())
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
@@ -5033,9 +5098,11 @@
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ZCR_EL3)
+ .reset(sveVL - 1)
.fault(EL3, faultZcrEL3)
.mon();
InitReg(MISCREG_ZCR_EL2)
+ .reset(sveVL - 1)
.fault(EL2, faultZcrEL2)
.fault(EL3, faultZcrEL3)
.hyp().mon();
@@ -5044,6 +5111,7 @@
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_ZCR_EL1);
InitReg(MISCREG_ZCR_EL1)
+ .reset(sveVL - 1)
.fault(EL1, faultZcrEL1)
.fault(EL2, faultZcrEL2)
.fault(EL3, faultZcrEL3)
@@ -5051,22 +5119,77 @@
// SME
InitReg(MISCREG_ID_AA64SMFR0_EL1)
+ .reset([](){
+ AA64SMFR0 smfr0_el1 = 0;
+ smfr0_el1.f32f32 = 0x1;
+ // The following BF16F32 is actually not implemented due to a
+ // lack of BF16 support in gem5's fplib. However, as per the
+ // SME spec the _only_ allowed value is 0x1.
+ smfr0_el1.b16f32 = 0x1;
+ smfr0_el1.f16f32 = 0x1;
+ smfr0_el1.i8i32 = 0xF;
+ smfr0_el1.f64f64 = 0x1;
+ smfr0_el1.i16i64 = 0xF;
+ smfr0_el1.smEver = 0;
+ smfr0_el1.fa64 = 0x1;
+ return smfr0_el1;
+ }())
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_SVCR)
.allPrivileges();
InitReg(MISCREG_SMIDR_EL1)
+ .reset([](){
+ SMIDR smidr_el1 = 0;
+ smidr_el1.affinity = 0;
+ smidr_el1.smps = 0;
+ smidr_el1.implementer = 0x41;
+ return smidr_el1;
+ }())
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_SMPRI_EL1)
.allPrivileges().exceptUserMode().reads(1);
InitReg(MISCREG_SMPRIMAP_EL2)
.hyp().mon();
InitReg(MISCREG_SMCR_EL3)
+ .reset([this](){
+ // We want to support FEAT_SME_FA64. Therefore, we enable it in
+ // all SMCR_ELx registers by default. Runtime software might
+ // change this later, but given that gem5 doesn't disable
+ // instructions based on this flag we default to the most
+ // representative value.
+ SMCR smcr_el3 = 0;
+ smcr_el3.fa64 = 1;
+ smcr_el3.len = smeVL - 1;
+ return smcr_el3;
+ }())
.mon();
InitReg(MISCREG_SMCR_EL2)
+ .reset([this](){
+ // We want to support FEAT_SME_FA64. Therefore, we enable it in
+ // all SMCR_ELx registers by default. Runtime software might
+ // change this later, but given that gem5 doesn't disable
+ // instructions based on this flag we default to the most
+ // representative value.
+ SMCR smcr_el2 = 0;
+ smcr_el2.fa64 = 1;
+ smcr_el2.len = smeVL - 1;
+ return smcr_el2;
+ }())
.hyp().mon();
InitReg(MISCREG_SMCR_EL12)
.allPrivileges().exceptUserMode();
InitReg(MISCREG_SMCR_EL1)
+ .reset([this](){
+ // We want to support FEAT_SME_FA64. Therefore, we enable it in
+ // all SMCR_ELx registers by default. Runtime software might
+ // change this later, but given that gem5 doesn't disable
+ // instructions based on this flag we default to the most
+ // representative value.
+ SMCR smcr_el1 = 0;
+ smcr_el1.fa64 = 1;
+ smcr_el1.len = smeVL - 1;
+ return smcr_el1;
+ }())
.allPrivileges().exceptUserMode();
InitReg(MISCREG_TPIDR2_EL0)
.allPrivileges();
--
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https://gem5-review.googlesource.com/c/public/gem5/+/70469?usp=email
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3d03ee15df46fa7d9a9ec439b26e99baf33cbb5e
Gerrit-Change-Number: 70469
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
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