Attention is currently required from: Richard Cooper.
Hello Richard Cooper,
I'd like you to do a code review.
Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/70459?usp=email
to review the following change.
Change subject: arch-arm: Generalize SCTLR_RST behaviour
......................................................................
arch-arm: Generalize SCTLR_RST behaviour
This is supposed to be employed as a reset value for SCTLR.
Rather than implementing this misc reg specific feature, we
provide a more general logic for changing the reset value
of any register.
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Change-Id: Ib61019ec499b35382289fe18740c90eee5de4907
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
4 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 5a0dec5..b0a856e 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2022 Arm Limited
+ * Copyright (c) 2010-2023 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -91,8 +91,6 @@
_regClasses.push_back(&ccRegClass);
_regClasses.push_back(&miscRegClass);
- miscRegs[MISCREG_SCTLR_RST] = 0;
-
// Hook up a dummy device if we haven't been configured with a
// real PMU. By using a dummy device, we don't need to check that
// the PMU exist every time we try to access a PMU register.
@@ -140,7 +138,6 @@
getMMUPtr(tc)->invalidateMiscReg();
}
- SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
for (auto idx = 0; idx < NUM_MISCREGS; idx++) {
miscRegs[idx] = lookUpMiscReg[idx].reset();
}
@@ -221,11 +218,11 @@
}
// Initialize AArch32 state...
- clear32(p, sctlr_rst);
+ clear32(p);
}
void
-ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
+ISA::clear32(const ArmISAParams &p)
{
CPSR cpsr = 0;
cpsr.mode = MODE_USER;
@@ -238,9 +235,6 @@
updateRegMap(cpsr);
SCTLR sctlr = 0;
- sctlr.te = (bool) sctlr_rst.te;
- sctlr.nmfi = (bool) sctlr_rst.nmfi;
- sctlr.v = (bool) sctlr_rst.v;
sctlr.u = 1;
sctlr.xp = 1;
sctlr.rao2 = 1;
@@ -249,7 +243,6 @@
sctlr.uci = 1;
sctlr.dze = 1;
miscRegs[MISCREG_SCTLR_NS] = sctlr;
- miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
miscRegs[MISCREG_HCPTR] = 0;
miscRegs[MISCREG_CPACR] = 0;
@@ -2084,6 +2077,20 @@
}
}
+RegVal
+ISA::readMiscRegReset(RegIndex idx) const
+{
+ int flat_idx = flattenMiscIndex(idx);
+ return lookUpMiscReg[flat_idx].reset();
+}
+
+void
+ISA::setMiscRegReset(RegIndex idx, RegVal val)
+{
+ int flat_idx = flattenMiscIndex(idx);
+ InitReg(flat_idx).reset(val);
+}
+
BaseISADevice &
ISA::getGenericTimer()
{
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 512799f..5dd1b38 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2022 ARM Limited
+ * Copyright (c) 2010, 2012-2023 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -170,7 +170,7 @@
void clear() override;
protected:
- void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst);
+ void clear32(const ArmISAParams &p);
void clear64(const ArmISAParams &p);
void initID32(const ArmISAParams &p);
void initID64(const ArmISAParams &p);
@@ -201,6 +201,9 @@
void setMiscRegNoEffect(RegIndex idx, RegVal val) override;
void setMiscReg(RegIndex, RegVal val) override;
+ RegVal readMiscRegReset(RegIndex) const;
+ void setMiscRegReset(RegIndex, RegVal val);
+
int
flattenMiscIndex(int reg) const
{
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 382b63e..e984164 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2196,8 +2196,6 @@
.bankedChild();
InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
.mutex();
- InitReg(MISCREG_SCTLR_RST)
- .allPrivileges();
InitReg(MISCREG_SEV_MAILBOX)
.allPrivileges();
InitReg(MISCREG_TLBINEEDSYNC)
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 69d1461..265a697 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -93,7 +93,6 @@
MISCREG_NMRR_MAIR1_NS,
MISCREG_NMRR_MAIR1_S,
MISCREG_PMXEVTYPER_PMCCFILTR,
- MISCREG_SCTLR_RST,
MISCREG_SEV_MAILBOX,
MISCREG_TLBINEEDSYNC,
@@ -1752,7 +1751,6 @@
"nmrr_mair1_ns",
"nmrr_mair1_s",
"pmxevtyper_pmccfiltr",
- "sctlr_rst",
"sev_mailbox",
"tlbi_needsync",
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib61019ec499b35382289fe18740c90eee5de4907
Gerrit-Change-Number: 70459
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Attention: Richard Cooper <richard.coo...@arm.com>
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