Roger Chang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/69937?usp=email )
Change subject: arch-riscv: Add RV32 only Zk instruction extensions
......................................................................
arch-riscv: Add RV32 only Zk instruction extensions
The following instructions is add:
Zbkb extension:
zip
unzip
Zknd extension:
aes32dsi
aes32dsmi
Zkne extension:
aes32esi
aes32esmi
Zknh extension:
sha512sig0h
sha512sig0l
sha512sig1h
sha512sig1l
sha512sum0r
sha512sum1r
Change-Id: Id29007704128154d9fb8305155f92c2e08ffa435
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69937
Maintainer: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Hoa Nguyen <hoangu...@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/rvk.hh
2 files changed, 114 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Hoa Nguyen: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index cb2b199..6f66c98 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -524,6 +524,11 @@
}
Rd = rvSext(Rs1 << imm);
}}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;
}});
+ 0x01: decode RVTYPE {
+ 0x0: zip({{
+ Rd_sw = _rvk_emu_zip_32(Rs1_sw);
+ }}, imm_code = {{ imm = SHAMT5; }});
+ }
0x02: decode FS2 {
0x0: sha256sum0({{
Rd_sw = _rvk_emu_sha256sum0(Rs1_sw);
@@ -643,6 +648,11 @@
}
Rd = rvSext(rvZext(Rs1) >> imm);
}}, imm_type = uint64_t, imm_code = {{ imm = SHAMT6;
}});
+ 0x1: decode RVTYPE {
+ 0x0: unzip({{
+ Rd_sw = _rvk_emu_unzip_32(Rs1_sw);
+ }}, imm_code = {{ imm = SHAMT5; }});
+ }
0x5: orc_b({{
uint64_t result = 0;
result |= (Rs1<7:0> ? UINT64_C(0xff) : 0x0);
@@ -991,6 +1001,68 @@
Rd = rvSext(Rs1_sd * Rs2_sd);
}}, IntMultOp);
}
+ 0x08: decode BS {
+ 0x1: decode RVTYPE {
+ 0x0: sha512sum0r({{
+ Rd_sw = _rvk_emu_sha512sum0r(Rs1_sw,
Rs2_sw);
+ }});
+ }
+ }
+ 0x09: decode BS {
+ 0x1: decode RVTYPE {
+ 0x0: sha512sum1r({{
+ Rd_sw = _rvk_emu_sha512sum1r(Rs1_sw,
Rs2_sw);
+ }});
+ }
+ }
+ 0x0a: decode BS {
+ 0x1: decode RVTYPE {
+ 0x0: sha512sig0l({{
+ Rd_sw = _rvk_emu_sha512sig0l(Rs1_sw,
Rs2_sw);
+ }});
+ }
+ }
+ 0x0b: decode BS {
+ 0x1: decode RVTYPE {
+ 0x0: sha512sig1l({{
+ Rd_sw = _rvk_emu_sha512sig1l(Rs1_sw,
Rs2_sw);
+ }});
+ }
+ }
+ 0x0e: decode BS {
+ 0x1: decode RVTYPE {
+ 0x0: sha512sig0h({{
+ Rd_sw = _rvk_emu_sha512sig0h(Rs1_sw,
Rs2_sw);
+ }});
+ }
+ }
+ 0x0f: decode BS {
+ 0x1: decode RVTYPE {
+ 0x0: sha512sig1h({{
+ Rd_sw = _rvk_emu_sha512sig1h(Rs1_sw,
Rs2_sw);
+ }});
+ }
+ }
+ 0x11: decode RVTYPE {
+ 0x0: aes32esi({{
+ Rd_sw = _rvk_emu_aes32esi(Rs1_sw, Rs2_sw,
(uint8_t)BS);
+ }});
+ }
+ 0x13: decode RVTYPE {
+ 0x0: aes32esmi({{
+ Rd_sw = _rvk_emu_aes32esmi(Rs1_sw, Rs2_sw,
(uint8_t)BS);
+ }});
+ }
+ 0x15: decode RVTYPE {
+ 0x0: aes32dsi({{
+ Rd_sw = _rvk_emu_aes32dsi(Rs1_sw, Rs2_sw,
(uint8_t)BS);
+ }});
+ }
+ 0x17: decode RVTYPE {
+ 0x0: aes32dsmi({{
+ Rd_sw = _rvk_emu_aes32dsmi(Rs1_sw, Rs2_sw,
(uint8_t)BS);
+ }});
+ }
0x18: sm4ed({{
Rd_sw = _rvk_emu_sm4ed(Rs1_sw, Rs2_sw,
(uint8_t)BS);
}});
diff --git a/src/arch/riscv/rvk.hh b/src/arch/riscv/rvk.hh
index d4af3cd..678359c 100644
--- a/src/arch/riscv/rvk.hh
+++ b/src/arch/riscv/rvk.hh
@@ -525,6 +525,48 @@
return (int32_t) x;
}
+static inline int32_t _rvk_emu_sha512sig0h(int32_t rs1, int32_t rs2)
+{
+ return _rvk_emu_srl_32(rs1, 1) ^ _rvk_emu_srl_32(rs1, 7) ^
+ _rvk_emu_srl_32(rs1, 8) ^ _rvk_emu_sll_32(rs2, 31) ^
+ _rvk_emu_sll_32(rs2, 24);
+}
+
+static inline int32_t _rvk_emu_sha512sig0l(int32_t rs1, int32_t rs2)
+{
+ return _rvk_emu_srl_32(rs1, 1) ^ _rvk_emu_srl_32(rs1, 7) ^
+ _rvk_emu_srl_32(rs1, 8) ^ _rvk_emu_sll_32(rs2, 31) ^
+ _rvk_emu_sll_32(rs2, 25) ^ _rvk_emu_sll_32(rs2, 24);
+}
+
+static inline int32_t _rvk_emu_sha512sig1h(int32_t rs1, int32_t rs2)
+{
+ return _rvk_emu_sll_32(rs1, 3) ^ _rvk_emu_srl_32(rs1, 6) ^
+ _rvk_emu_srl_32(rs1, 19) ^ _rvk_emu_srl_32(rs2, 29) ^
+ _rvk_emu_sll_32(rs2, 13);
+}
+
+static inline int32_t _rvk_emu_sha512sig1l(int32_t rs1, int32_t rs2)
+{
+ return _rvk_emu_sll_32(rs1, 3) ^ _rvk_emu_srl_32(rs1, 6) ^
+ _rvk_emu_srl_32(rs1,19) ^ _rvk_emu_srl_32(rs2, 29) ^
+ _rvk_emu_sll_32(rs2, 26) ^ _rvk_emu_sll_32(rs2, 13);
+}
+
+static inline int32_t _rvk_emu_sha512sum0r(int32_t rs1, int32_t rs2)
+{
+ return _rvk_emu_sll_32(rs1, 25) ^ _rvk_emu_sll_32(rs1, 30) ^
+ _rvk_emu_srl_32(rs1, 28) ^ _rvk_emu_srl_32(rs2, 7) ^
+ _rvk_emu_srl_32(rs2, 2) ^ _rvk_emu_sll_32(rs2, 4);
+}
+
+static inline int32_t _rvk_emu_sha512sum1r(int32_t rs1, int32_t rs2)
+{
+ return _rvk_emu_sll_32(rs1, 23) ^ _rvk_emu_srl_32(rs1,14) ^
+ _rvk_emu_srl_32(rs1, 18) ^ _rvk_emu_srl_32(rs2, 9) ^
+ _rvk_emu_sll_32(rs2, 18) ^ _rvk_emu_sll_32(rs2, 14);
+}
+
inline int64_t _rvk_emu_sha512sig0(int64_t rs1)
{
return _rvk_emu_ror_64(rs1, 1) ^ _rvk_emu_ror_64(rs1, 8) ^
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id29007704128154d9fb8305155f92c2e08ffa435
Gerrit-Change-Number: 69937
Gerrit-PatchSet: 7
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-Reviewer: Hoa Nguyen <hoangu...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Roger Chang <rogerycch...@google.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Yu-hsin Wang <yuhsi...@google.com>
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