Roger Chang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/66871?usp=email )
(
8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-riscv: Remove Riscv32CPU instance
......................................................................
arch-riscv: Remove Riscv32CPU instance
To use riscv 32 bits CPU, we can simply speficy by RiscvXXXCPU
parameters like
RiscvAtomicSimpleCPU(isa=RiscvISA(riscv_type="RV32"...))
Change-Id: I7ec66957f978062eda609b1a7e63468d23b5bab5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66871
Reviewed-by: Jui-min Lee <f...@google.com>
Maintainer: Bobby Bruce <bbr...@ucdavis.edu>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Bobby Bruce <bbr...@ucdavis.edu>
Reviewed-by: Yu-hsin Wang <yuhsi...@google.com>
---
M src/arch/riscv/RiscvCPU.py
1 file changed, 0 insertions(+), 29 deletions(-)
Approvals:
kokoro: Regressions pass
Jui-min Lee: Looks good to me, but someone else must approve
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
Yu-hsin Wang: Looks good to me, approved
diff --git a/src/arch/riscv/RiscvCPU.py b/src/arch/riscv/RiscvCPU.py
index 678c329..1c77045 100644
--- a/src/arch/riscv/RiscvCPU.py
+++ b/src/arch/riscv/RiscvCPU.py
@@ -23,8 +23,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-import functools
-
from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
@@ -43,13 +41,6 @@
ArchISA = RiscvISA
-class Riscv32CPU:
- ArchDecoder = RiscvDecoder
- ArchMMU = RiscvMMU
- ArchInterrupts = RiscvInterrupts
- ArchISA = functools.partial(RiscvISA, riscv_type="RV32")
-
-
class RiscvAtomicSimpleCPU(BaseAtomicSimpleCPU, RiscvCPU):
mmu = RiscvMMU()
@@ -68,23 +59,3 @@
class RiscvMinorCPU(BaseMinorCPU, RiscvCPU):
mmu = RiscvMMU()
-
-
-class Riscv32AtomicSimpleCPU(BaseAtomicSimpleCPU, Riscv32CPU):
- mmu = RiscvMMU()
-
-
-class Riscv32NonCachingSimpleCPU(BaseNonCachingSimpleCPU, Riscv32CPU):
- mmu = RiscvMMU()
-
-
-class Riscv32TimingSimpleCPU(BaseTimingSimpleCPU, Riscv32CPU):
- mmu = RiscvMMU()
-
-
-class Riscv32O3CPU(BaseO3CPU, Riscv32CPU):
- mmu = RiscvMMU()
-
-
-class Riscv32MinorCPU(BaseMinorCPU, Riscv32CPU):
- mmu = RiscvMMU()
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7ec66957f978062eda609b1a7e63468d23b5bab5
Gerrit-Change-Number: 66871
Gerrit-PatchSet: 11
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Jui-min Lee <f...@google.com>
Gerrit-Reviewer: Roger Chang <rogerycch...@google.com>
Gerrit-Reviewer: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Earl Ou <shunhsin...@google.com>
Gerrit-CC: Jason Lowe-Power <power...@gmail.com>
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