Wei-Han Chen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/69477?usp=email )
Change subject: systemc: Add AXI4 cache attributes entry in control
extension
......................................................................
systemc: Add AXI4 cache attributes entry in control extension
This CL adds the entry of AXI4 cache attributes in gem5
ControlExtension. It gives us an opportunity to bring this information /
take out this information from AXI4 world.
Change-Id: Icf451566da46c40e42677459c66fbf446bec6185
---
M src/systemc/tlm_bridge/sc_ext.cc
M src/systemc/tlm_bridge/sc_ext.hh
2 files changed, 92 insertions(+), 0 deletions(-)
diff --git a/src/systemc/tlm_bridge/sc_ext.cc
b/src/systemc/tlm_bridge/sc_ext.cc
index 6e3cf11..10daa9a 100644
--- a/src/systemc/tlm_bridge/sc_ext.cc
+++ b/src/systemc/tlm_bridge/sc_ext.cc
@@ -315,4 +315,76 @@
substream_id = std::move(s);
}
+bool
+ControlExtension::hasBufferable() const
+{
+ return bufferable.has_value();
+}
+
+std::optional<bool>
+ControlExtension::getBufferable() const
+{
+ return bufferable;
+}
+
+void
+ControlExtension::setBufferable(std::optional<bool> b)
+{
+ bufferable = std::move(b);
+}
+
+bool
+ControlExtension::hasModifiable() const
+{
+ return modifiable.has_value();
+}
+
+std::optional<bool>
+ControlExtension::getModifiable() const
+{
+ return modifiable;
+}
+
+void
+ControlExtension::setModifiable(std::optional<bool> m)
+{
+ modifiable = std::move(m);
+}
+
+bool
+ControlExtension::hasReadAllocate() const
+{
+ return read_allocate.has_value();
+}
+
+std::optional<bool>
+ControlExtension::getReadAllocate() const
+{
+ return read_allocate;
+}
+
+void
+ControlExtension::setReadAllocate(std::optional<bool> ra)
+{
+ read_allocate = std::move(ra);
+}
+
+bool
+ControlExtension::hasWriteAllocate() const
+{
+ return write_allocate.has_value();
+}
+
+std::optional<bool>
+ControlExtension::getWriteAllocate() const
+{
+ return write_allocate;
+}
+
+void
+ControlExtension::setWriteAllocate(std::optional<bool> wa)
+{
+ write_allocate = std::move(wa);
+}
+
} // namespace Gem5SystemC
diff --git a/src/systemc/tlm_bridge/sc_ext.hh
b/src/systemc/tlm_bridge/sc_ext.hh
index f23f3fa..96e679c 100644
--- a/src/systemc/tlm_bridge/sc_ext.hh
+++ b/src/systemc/tlm_bridge/sc_ext.hh
@@ -124,6 +124,20 @@
std::optional<uint32_t> getSubstreamId() const;
void setSubstreamId(std::optional<uint32_t> s);
+ /* AXI4 Cache Attributes */
+ bool hasBufferable() const;
+ std::optional<bool> getBufferable() const;
+ void setBufferable(std::optional<bool> b);
+ bool hasModifiable() const;
+ std::optional<bool> getModifiable() const;
+ void setModifiable(std::optional<bool> m);
+ bool hasReadAllocate() const;
+ std::optional<bool> getReadAllocate() const;
+ void setReadAllocate(std::optional<bool> ra);
+ bool hasWriteAllocate() const;
+ std::optional<bool> getWriteAllocate() const;
+ void setWriteAllocate(std::optional<bool> wa);
+
private:
/* Secure and privileged access */
bool privileged;
@@ -136,6 +150,12 @@
/* Stream ID and Substream ID */
std::optional<uint32_t> stream_id;
std::optional<uint32_t> substream_id;
+
+ /* AXI4 Cache Attributes */
+ std::optional<bool> bufferable;
+ std::optional<bool> modifiable;
+ std::optional<bool> read_allocate;
+ std::optional<bool> write_allocate;
};
} // namespace Gem5SystemC
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icf451566da46c40e42677459c66fbf446bec6185
Gerrit-Change-Number: 69477
Gerrit-PatchSet: 1
Gerrit-Owner: Wei-Han Chen <weihanc...@google.com>
Gerrit-MessageType: newchange
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