VISHNU RAMADAS has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/69298?usp=email )
Change subject: dev-amdgpu: Added PM4MapQueues to GPUFS checkpoint
......................................................................
dev-amdgpu: Added PM4MapQueues to GPUFS checkpoint
The GPUFS checkpoint restoration mechanism expects to find a
PM4MapQueues packet in the checkpoint. Since this was not being
checkpointed, the restore phase retrieved a null packet which led to a
segmentation fault. This commit adds PM4MapQueues to the checkpoint and
restores it when deserializing the checkpoint
Change-Id: Ib74a9f36fe89d740a74f94314ada41ecc363abe9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69298
Reviewed-by: Matt Sinclair <mattdsincl...@gmail.com>
Maintainer: Matt Sinclair <mattdsincl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Matthew Poremba <matthew.pore...@amd.com>
---
M src/dev/amdgpu/pm4_packet_processor.cc
M src/dev/amdgpu/pm4_queues.hh
2 files changed, 33 insertions(+), 2 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, but someone else must approve; Looks
good to me, approved
Matthew Poremba: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/amdgpu/pm4_packet_processor.cc
b/src/dev/amdgpu/pm4_packet_processor.cc
index 152fd4d..071fe8b 100644
--- a/src/dev/amdgpu/pm4_packet_processor.cc
+++ b/src/dev/amdgpu/pm4_packet_processor.cc
@@ -1021,6 +1021,10 @@
Addr offset[num_queues];
bool processing[num_queues];
bool ib[num_queues];
+ uint32_t me[num_queues];
+ uint32_t pipe[num_queues];
+ uint32_t queue[num_queues];
+ bool privileged[num_queues];
int i = 0;
for (auto iter : queues) {
@@ -1040,6 +1044,10 @@
offset[i] = q->offset();
processing[i] = q->processing();
ib[i] = q->ib();
+ me[i] = q->me();
+ pipe[i] = q->pipe();
+ queue[i] = q->queue();
+ privileged[i] = q->privileged();
i++;
}
@@ -1055,6 +1063,10 @@
SERIALIZE_ARRAY(offset, num_queues);
SERIALIZE_ARRAY(processing, num_queues);
SERIALIZE_ARRAY(ib, num_queues);
+ SERIALIZE_ARRAY(me, num_queues);
+ SERIALIZE_ARRAY(pipe, num_queues);
+ SERIALIZE_ARRAY(queue, num_queues);
+ SERIALIZE_ARRAY(privileged, num_queues);
}
void
@@ -1077,6 +1089,10 @@
Addr offset[num_queues];
bool processing[num_queues];
bool ib[num_queues];
+ uint32_t me[num_queues];
+ uint32_t pipe[num_queues];
+ uint32_t queue[num_queues];
+ bool privileged[num_queues];
UNSERIALIZE_ARRAY(id, num_queues);
UNSERIALIZE_ARRAY(mqd_base, num_queues);
@@ -1089,6 +1105,10 @@
UNSERIALIZE_ARRAY(offset, num_queues);
UNSERIALIZE_ARRAY(processing, num_queues);
UNSERIALIZE_ARRAY(ib, num_queues);
+ UNSERIALIZE_ARRAY(me, num_queues);
+ UNSERIALIZE_ARRAY(pipe, num_queues);
+ UNSERIALIZE_ARRAY(queue, num_queues);
+ UNSERIALIZE_ARRAY(privileged, num_queues);
for (int i = 0; i < num_queues; i++) {
QueueDesc *mqd = new QueueDesc();
@@ -1100,7 +1120,9 @@
mqd->ibBase = ib_base[i];
mqd->ibRptr = ib_rptr[i];
- newQueue(mqd, offset[i], nullptr, id[i]);
+ PM4MapQueues* pkt = new PM4MapQueues;
+ memset(pkt, 0, sizeof(PM4MapQueues));
+ newQueue(mqd, offset[i], pkt, id[i]);
queues[id[i]]->ib(false);
queues[id[i]]->wptr(wptr[i]);
@@ -1109,6 +1131,8 @@
queues[id[i]]->offset(offset[i]);
queues[id[i]]->processing(processing[i]);
queues[id[i]]->ib(ib[i]);
+ queues[id[i]]->setPkt(me[i], pipe[i], queue[i], privileged[i]);
+
DPRINTF(PM4PacketProcessor, "PM4 queue %d, rptr: %p wptr: %p\n",
queues[id[i]]->id(), queues[id[i]]->rptr(),
queues[id[i]]->wptr());
diff --git a/src/dev/amdgpu/pm4_queues.hh b/src/dev/amdgpu/pm4_queues.hh
index ddadd65..9c99e10 100644
--- a/src/dev/amdgpu/pm4_queues.hh
+++ b/src/dev/amdgpu/pm4_queues.hh
@@ -391,7 +391,7 @@
Addr _offset;
bool _processing;
bool _ib;
- const PM4MapQueues _pkt;
+ PM4MapQueues _pkt;
public:
PM4Queue() : _id(0), q(nullptr), _wptr(0), _offset(0),
_processing(false),
_ib(false), _pkt() {}
@@ -486,6 +486,13 @@
uint32_t pipe() { return _pkt.pipe; }
uint32_t queue() { return _pkt.queueSlot; }
bool privileged() { return _pkt.queueSel == 0 ? 1 : 0; }
+ PM4MapQueues* getPkt() { return &_pkt; }
+ void setPkt(uint32_t me, uint32_t pipe, uint32_t queue, bool
privileged) {
+ _pkt.me = me - 1;
+ _pkt.pipe = pipe;
+ _pkt.queueSlot = queue;
+ _pkt.queueSel = (privileged == 0) ? 1 : 0;
+ }
// Same computation as processMQD. See comment there for details.
uint64_t size() { return 4UL << ((q->hqd_pq_control & 0x3f) + 1); }
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib74a9f36fe89d740a74f94314ada41ecc363abe9
Gerrit-Change-Number: 69298
Gerrit-PatchSet: 3
Gerrit-Owner: VISHNU RAMADAS <vrama...@wisc.edu>
Gerrit-Reviewer: Matt Sinclair <mattdsincl...@gmail.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: VISHNU RAMADAS <vrama...@wisc.edu>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Matt Sinclair <mattdsinclair.w...@gmail.com>
Gerrit-MessageType: merged
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