Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/68917?usp=email )
Change subject: arch-riscv: Add new misa bit union
......................................................................
arch-riscv: Add new misa bit union
The new misa bit union type can help get and set misa CSR more
clearily
Change-Id: Id48b140968a0e8021b09782815aa612b409ac75b
---
M src/arch/riscv/isa.cc
M src/arch/riscv/regs/misc.hh
2 files changed, 60 insertions(+), 16 deletions(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 7964de5..18e1d7e 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -287,21 +287,33 @@
miscRegFile[MISCREG_VENDORID] = 0;
miscRegFile[MISCREG_ARCHID] = 0;
miscRegFile[MISCREG_IMPID] = 0;
+
+ MISA misa = 0;
+ STATUS status = 0;
+
// rv_type dependent init.
- switch (rv_type) {
+ // default config arch isa string is rv64(32)imafdc
+ misa.rvi = misa.rvm = misa.rva = misa.rvf = misa.rvd = misa.rvc = 1;
+ // default privlege modes if MSU
+ misa.rvs = misa.rvu = 1;
+
+ // mark FS is initial
+ status.fs = INITIAL;
+
+ switch(rv_type) {
case RV32:
- miscRegFile[MISCREG_ISA] = (1ULL << MXL_OFFSETS[RV32]) |
0x14112D;
- miscRegFile[MISCREG_STATUS] = (1ULL << FS_OFFSET);
- break;
+ misa.rv32_mxl = 1;
+ break;
case RV64:
- miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSETS[RV64]) |
0x14112D;
- miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) |
- (2ULL << SXL_OFFSET) |
- (1ULL << FS_OFFSET);
- break;
+ misa.rv64_mxl = 2;
+ status.uxl = status.sxl = 2;
+ break;
default:
- panic("%s: Unknown rv_type: %d", name(), (int)rv_type);
+ panic("%s: Unknown rv_type: %d", name(), (int)rv_type);
}
+
+ miscRegFile[MISCREG_ISA] = misa;
+ miscRegFile[MISCREG_STATUS] = status;
miscRegFile[MISCREG_MCOUNTEREN] = 0x7;
miscRegFile[MISCREG_SCOUNTEREN] = 0x7;
// don't set it to zero; software may try to determine the supported
@@ -425,10 +437,10 @@
case MISCREG_SEPC:
case MISCREG_MEPC:
{
- auto misa = readMiscRegNoEffect(MISCREG_ISA);
+ MISA misa = readMiscRegNoEffect(MISCREG_ISA);
auto val = readMiscRegNoEffect(idx);
// if compressed instructions are disabled, epc[1] is set to 0
- if ((misa & ISA_EXT_C_MASK) == 0)
+ if (misa.rvc == 0)
return mbits(val, 63, 2);
// epc[0] is always 0
else
@@ -617,15 +629,16 @@
break;
case MISCREG_ISA:
{
- auto cur_val = readMiscRegNoEffect(idx);
+ MISA cur_misa = (MISA)readMiscRegNoEffect(MISCREG_ISA);
+ MISA new_misa = (MISA)val;
// only allow to disable compressed instructions
// if the following instruction is 4-byte aligned
- if ((val & ISA_EXT_C_MASK) == 0 &&
+ if (new_misa.rvc == 0 &&
bits(tc->pcState().as<RiscvISA::PCState>().npc(),
2, 0) != 0) {
- val |= cur_val & ISA_EXT_C_MASK;
+ new_misa.rvc = new_misa.rvc | cur_misa.rvc;
}
- setMiscRegNoEffect(idx, val);
+ setMiscRegNoEffect(idx, new_misa);
}
break;
case MISCREG_STATUS:
diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh
index 8cb4ca0..d12b40d 100644
--- a/src/arch/riscv/regs/misc.hh
+++ b/src/arch/riscv/regs/misc.hh
@@ -754,6 +754,37 @@
/**
* These fields are specified in the RISC-V Instruction Set Manual, Volume
II,
+ * v1.10, v1.11 and v.12 in Figure 3.1, accessible at www.riscv.org. The
register
+ * is used to control instruction extensions.
+ */
+BitUnion64(MISA)
+ Bitfield<63, 62> rv64_mxl;
+ Bitfield<31, 30> rv32_mxl;
+ Bitfield<23> rvx;
+ Bitfield<21> rvv;
+ Bitfield<20> rvu;
+ Bitfield<19> rvt;
+ Bitfield<18> rvs;
+ Bitfield<16> rvq;
+ Bitfield<15> rvp;
+ Bitfield<13> rvn;
+ Bitfield<12> rvm;
+ Bitfield<11> rvl;
+ Bitfield<10> rvk;
+ Bitfield<9> rvj;
+ Bitfield<8> rvi;
+ Bitfield<7> rvh;
+ Bitfield<6> rvg;
+ Bitfield<5> rvf;
+ Bitfield<4> rve;
+ Bitfield<3> rvd;
+ Bitfield<2> rvc;
+ Bitfield<1> rvb;
+ Bitfield<0> rva;
+EndBitUnion(MISA)
+
+/**
+ * These fields are specified in the RISC-V Instruction Set Manual, Volume
II,
* v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the
MIP
* and MIE registers have the same fields, so accesses to either should use
* this bit union.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id48b140968a0e8021b09782815aa612b409ac75b
Gerrit-Change-Number: 68917
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-MessageType: newchange
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