Melissa Jost has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/68637?usp=email )
Change subject: arch-riscv: Revert CSR instruction fixes
......................................................................
arch-riscv: Revert CSR instruction fixes
This reverts commit 4b1c24542065380c6cff7ab2baa25e216a0ad38e
and commit 89c49d1ab06ea5364ab1f80586f8b01c0297cb12 because
they are causing the RISC-V Ubuntu boot test within the
nightly tests to hang and time out.
Change-Id: Ia4d8098ec940cb5900256c8cede0146256c851e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68637
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Roger Chang <rogerycch...@google.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
---
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/formats/standard.isa
2 files changed, 8 insertions(+), 26 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Roger Chang: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/insts/standard.hh
b/src/arch/riscv/insts/standard.hh
index 2dfe73a..5b0e8c2 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -91,33 +91,18 @@
protected:
uint64_t csr;
uint64_t uimm;
- bool read;
- bool write;
/// Constructor
CSROp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: RiscvStaticInst(mnem, _machInst, __opClass),
- csr(FUNCT12), uimm(CSRIMM), read(true), write(true)
+ csr(FUNCT12), uimm(CSRIMM)
{
if (csr == CSR_SATP) {
flags[IsSquashAfter] = true;
}
- if (strcmp(mnemonic, "csrrw") == 0 ||
- strcmp(mnemonic, "csrrwi") == 0) {
- if (RD == 0){
- read = false;
- }
- } else if (strcmp(mnemonic, "csrrs") == 0 ||
- strcmp(mnemonic, "csrrc") == 0 ||
- strcmp(mnemonic, "csrrsi") == 0 ||
- strcmp(mnemonic, "csrrci") == 0 ){
- if (RS1 == 0 || uimm == 0) {
- write = false;
- }
- }
}
- std::string generateDisassembly(
+ std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
};
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index c94a0bc..bb500f5 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -358,7 +358,7 @@
%(op_decl)s;
%(op_rd)s;
- RegVal data = 0, olddata = 0, nonmaskdata = 0;
+ RegVal data, olddata;
auto lowestAllowedMode = (PrivilegeMode)bits(csr, 9, 8);
auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
if (pm < lowestAllowedMode) {
@@ -380,13 +380,11 @@
break;
}
- if (read) {
- if (csr == CSR_FCSR) {
+ if (csr == CSR_FCSR) {
olddata = xc->readMiscReg(MISCREG_FFLAGS) |
- (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
- } else {
+ (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
+ } else {
olddata = xc->readMiscReg(midx);
- }
}
olddata = rvZext(olddata);
auto olddata_all = olddata;
@@ -397,9 +395,8 @@
%(code)s;
- nonmaskdata = data & ~maskVal;
data &= maskVal;
- if (write) {
+ if (data != olddata) {
if (bits(csr, 11, 10) == 0x3) {
return std::make_shared<IllegalInstFault>(
csprintf("CSR %s is read-only\n", csrName),
machInst);
@@ -420,7 +417,7 @@
case CSR_SIP: case CSR_SIE:
case CSR_UIP: case CSR_UIE:
case CSR_MSTATUS: case CSR_SSTATUS: case CSR_USTATUS:
- if (nonmaskdata == 0) {
+ if (newdata_all != olddata_all) {
xc->setMiscReg(midx, newdata_all);
} else {
return std::make_shared<IllegalInstFault>(
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia4d8098ec940cb5900256c8cede0146256c851e5
Gerrit-Change-Number: 68637
Gerrit-PatchSet: 2
Gerrit-Owner: Melissa Jost <melissakj...@gmail.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Melissa Jost <mkj...@ucdavis.edu>
Gerrit-Reviewer: Roger Chang <rogerycch...@google.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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