Alex Richardson has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68481?usp=email )

Change subject: arch-riscv: Pretend that the UART is compatible with ns16550a
......................................................................

arch-riscv: Pretend that the UART is compatible with ns16550a

This is required to get output from bbl and should be fine since it
won't use any of the missing features.

Change-Id: I3add3cdb96da43b7d6fe4555d10b8c42d6736f06
---
M src/dev/serial/Uart.py
M src/python/gem5/components/boards/riscv_board.py
M src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
3 files changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/dev/serial/Uart.py b/src/dev/serial/Uart.py
index 2ca68b8..fb0d91e 100644
--- a/src/dev/serial/Uart.py
+++ b/src/dev/serial/Uart.py
@@ -82,5 +82,5 @@
         node.append(FdtPropertyWords("interrupts", [platform.uart_int_id]))
         node.append(FdtPropertyWords("clock-frequency", [0x384000]))
node.append(FdtPropertyWords("interrupt-parent", state.phandle(plic)))
-        node.appendCompatible(["ns8250"])
+        node.appendCompatible(["ns8250", "ns16550a"])
         yield node
diff --git a/src/python/gem5/components/boards/riscv_board.py b/src/python/gem5/components/boards/riscv_board.py
index 15ec57a..ca93a94 100644
--- a/src/python/gem5/components/boards/riscv_board.py
+++ b/src/python/gem5/components/boards/riscv_board.py
@@ -432,7 +432,7 @@
         uart_node.append(
             FdtPropertyWords("interrupt-parent", soc_state.phandle(plic))
         )
-        uart_node.appendCompatible(["ns8250"])
+        uart_node.appendCompatible(["ns8250", "ns16550a"])
         soc_node.append(uart_node)

         # VirtIO MMIO disk node
diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
index 4148c0a..5a40253 100644
--- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
+++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
@@ -504,7 +504,7 @@
         uart_node.append(
             FdtPropertyWords("interrupt-parent", soc_state.phandle(plic))
         )
-        uart_node.appendCompatible(["ns8250"])
+        uart_node.appendCompatible(["ns8250", "ns16550a"])
         soc_node.append(uart_node)

         # VirtIO MMIO disk node

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3add3cdb96da43b7d6fe4555d10b8c42d6736f06
Gerrit-Change-Number: 68481
Gerrit-PatchSet: 1
Gerrit-Owner: Alex Richardson <alexrichard...@google.com>
Gerrit-MessageType: newchange
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