轩胡 has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/68421?usp=email )
Change subject: arch-riscv: simplify implementation of multiply insts
......................................................................
arch-riscv: simplify implementation of multiply insts
Change-Id: I9e9d5252256f0453c9c4897717748d45e138cb9b
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 12 insertions(+), 54 deletions(-)
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index ddaf233..84ae243 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1278,27 +1278,7 @@
Rd_sw = ((int64_t)Rs1_sw * Rs2_sw) >> 32;
}}, IntMultOp);
0x1: mulh({{
- bool negate = (Rs1_sd < 0) != (Rs2_sd < 0);
-
- uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd);
- uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd)
32;
- uint64_t Rs2_lo = (uint32_t)std::abs(Rs2_sd);
- uint64_t Rs2_hi = (uint64_t)std::abs(Rs2_sd)
32;
-
- uint64_t hi = Rs1_hi*Rs2_hi;
- uint64_t mid1 = Rs1_hi*Rs2_lo;
- uint64_t mid2 = Rs1_lo*Rs2_hi;
- uint64_t lo = Rs2_lo*Rs1_lo;
- uint64_t carry = ((uint64_t)(uint32_t)mid1
- + (uint64_t)(uint32_t)mid2
- + (lo >> 32)) >> 32;
-
- uint64_t res = hi +
- (mid1 >> 32) +
- (mid2 >> 32) +
- carry;
- Rd = negate ? ~res + (Rs1_sd*Rs2_sd == 0 ? 1 :
0)
- : res;
+ Rd_sd = mulh(Rs1_sd, Rs2_sd);
}}, IntMultOp);
}
0x5: clmul({{
@@ -1338,25 +1318,7 @@
Rd_sw = ((int64_t)Rs1_sw * Rs2_uw) >> 32;
}}, IntMultOp);
0x1: mulhsu({{
- bool negate = Rs1_sd < 0;
- uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd);
- uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd)
32;
- uint64_t Rs2_lo = (uint32_t)Rs2;
- uint64_t Rs2_hi = Rs2 >> 32;
-
- uint64_t hi = Rs1_hi*Rs2_hi;
- uint64_t mid1 = Rs1_hi*Rs2_lo;
- uint64_t mid2 = Rs1_lo*Rs2_hi;
- uint64_t lo = Rs1_lo*Rs2_lo;
- uint64_t carry = ((uint64_t)(uint32_t)mid1
- + (uint64_t)(uint32_t)mid2
- + (lo >> 32)) >> 32;
-
- uint64_t res = hi +
- (mid1 >> 32) +
- (mid2 >> 32) +
- carry;
- Rd = negate ? ~res + (Rs1_sd*Rs2 == 0 ? 1 :
0) : res;
+ Rd_sd = mulhsu(Rs1_sd, Rs2);
}}, IntMultOp);
}
0x5: clmulr({{
@@ -1386,20 +1348,7 @@
Rd_sw = ((uint64_t)Rs1_uw * Rs2_uw) >> 32;
}}, IntMultOp);
0x1: mulhu({{
- uint64_t Rs1_lo = (uint32_t)Rs1;
- uint64_t Rs1_hi = Rs1 >> 32;
- uint64_t Rs2_lo = (uint32_t)Rs2;
- uint64_t Rs2_hi = Rs2 >> 32;
-
- uint64_t hi = Rs1_hi*Rs2_hi;
- uint64_t mid1 = Rs1_hi*Rs2_lo;
- uint64_t mid2 = Rs1_lo*Rs2_hi;
- uint64_t lo = Rs1_lo*Rs2_lo;
- uint64_t carry = ((uint64_t)(uint32_t)mid1
- + (uint64_t)(uint32_t)mid2
- + (lo >> 32)) >> 32;
-
- Rd = hi + (mid1 >> 32) + (mid2 >> 32) + carry;
+ Rd = mulhu(Rs1, Rs2);
}}, IntMultOp);
}
0x5: clmulh({{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9e9d5252256f0453c9c4897717748d45e138cb9b
Gerrit-Change-Number: 68421
Gerrit-PatchSet: 1
Gerrit-Owner: 轩胡 <huxuan0...@gmail.com>
Gerrit-MessageType: newchange
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