Derek C. has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/68218?usp=email )
Change subject: mem: Split up DRAMSysWrapper
......................................................................
mem: Split up DRAMSysWrapper
Split up DRAMSysWrapper into a SystemC wrapper and an AbstractMemory
implementor
Change-Id: Ia409eafc6e94529f887016db043e98e7dd80bf5e
---
M configs/example/dramsys/dramsys.py
M configs/example/gem5_library/dramsys.py
M ext/dramsys/README
M src/mem/DRAMSys.py
A src/mem/dramsys.hh
M src/mem/dramsys_wrapper.cc
M src/mem/dramsys_wrapper.hh
M src/python/gem5/components/memory/__init__.py
M src/python/gem5/components/memory/dramsys.py
9 files changed, 123 insertions(+), 62 deletions(-)
diff --git a/configs/example/dramsys/dramsys.py
b/configs/example/dramsys/dramsys.py
index 0ec21e8..d58019f 100755
--- a/configs/example/dramsys/dramsys.py
+++ b/configs/example/dramsys/dramsys.py
@@ -31,22 +31,23 @@
traffic_gen = PyTrafficGen()
system = System()
-vd = VoltageDomain(voltage = '1V')
+vd = VoltageDomain(voltage="1V")
-system.mem_mode = 'timing'
+system.mem_mode = "timing"
system.cpu = traffic_gen
system.target = DRAMSys(
- configuration = "ext/dramsys/DRAMSys/DRAMSys/"
- "library/resources/simulations/ddr4-example.json",
- resource_directory = "ext/dramsys/DRAMSys/DRAMSys/library/resources")
-system.physmem = SimpleMemory() # This must be instanciated, even if not
needed
+ configuration="ext/dramsys/DRAMSys/DRAMSys/"
+ "library/resources/simulations/ddr4-example.json",
+ resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
+)
+
system.transactor = Gem5ToTlmBridge32()
-system.clk_domain = SrcClockDomain(clock = '1.5GHz', voltage_domain = vd)
+system.clk_domain = SrcClockDomain(clock="1.5GHz", voltage_domain=vd)
# Connect everything:
system.transactor.gem5 = system.cpu.port
-system.transactor.tlm = system.target.tlm
+system.transactor.tlm = system.target.port
kernel = SystemC_Kernel(system=system)
root = Root(full_system=False, systemc_kernel=kernel)
diff --git a/configs/example/gem5_library/dramsys.py
b/configs/example/gem5_library/dramsys.py
index b844861..09bf546 100644
--- a/configs/example/gem5_library/dramsys.py
+++ b/configs/example/gem5_library/dramsys.py
@@ -27,19 +27,19 @@
"""
"""
-from gem5.components.memory import DRAMSysMemCtrl
+from gem5.components.memory import DRAMSysMem
from gem5.components.boards.test_board import TestBoard
from gem5.simulate.simulator import Simulator
from gem5.components.processors.linear_generator import LinearGenerator
from m5.objects import Root
import m5
-memory = DRAMSysMemCtrl(
+memory = DRAMSysMem(
configuration="ext/dramsys/DRAMSys/DRAMSys/"
"library/resources/simulations/ddr4-example.json",
+ size="4GB",
resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
recordable=True,
- size="4GB",
)
generator = LinearGenerator(
@@ -48,12 +48,15 @@
num_cores=1,
max_addr=memory.get_size(),
)
+
board = TestBoard(
clk_freq="3GHz", generator=generator, memory=memory,
cache_hierarchy=None
)
root = Root(full_system=False, system=board)
+
board._pre_instantiate()
m5.instantiate()
+
generator.start_traffic()
exit_event = m5.simulate()
diff --git a/ext/dramsys/README b/ext/dramsys/README
index ed429d1..fef580e 100644
--- a/ext/dramsys/README
+++ b/ext/dramsys/README
@@ -2,3 +2,4 @@
1 Go to ext/dramsys (this directory)
2 Clone DRAMSys: 'git clone --recursive
g...@github.com:tukl-msd/DRAMSys.git DRAMSys'
+3 Checkout the correct commit: 'git checkout -b gem5
09f6dcbb91351e6ee7cadfc7bc8b29d97625db8f'
diff --git a/src/mem/DRAMSys.py b/src/mem/DRAMSys.py
index 67bd97f..15122e5 100644
--- a/src/mem/DRAMSys.py
+++ b/src/mem/DRAMSys.py
@@ -24,11 +24,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from m5.SimObject import SimObject
+from m5.SimObject import *
from m5.params import *
from m5.proxy import *
-from m5.objects.SystemC import SystemC_ScModule
from m5.objects.Tlm import TlmTargetSocket
from m5.objects.AbstractMemory import *
@@ -36,9 +35,9 @@
# that work is handled in the base classes.
class DRAMSys(AbstractMemory):
type = "DRAMSys"
- cxx_class = "gem5::memory::DRAMSysWrapper"
- cxx_header = "mem/dramsys_wrapper.hh"
- tlm = TlmTargetSocket(32, "TLM target socket")
+ cxx_class = "gem5::memory::DRAMSys"
+ cxx_header = "mem/dramsys.hh"
+ port = TlmTargetSocket(32, "TLM target port")
configuration = Param.String("Path to the DRAMSys configuration.")
resource_directory = Param.String(
diff --git a/src/mem/dramsys.hh b/src/mem/dramsys.hh
new file mode 100644
index 0000000..0c4216d
--- /dev/null
+++ b/src/mem/dramsys.hh
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2022 Fraunhofer IESE
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MEM_DRAMSYS_H__
+#define __MEM_DRAMSYS_H__
+
+#include "DRAMSysConfiguration.h"
+#include "mem/abstract_mem.hh"
+#include "mem/dramsys_wrapper.hh"
+#include "params/DRAMSys.hh"
+
+namespace gem5
+{
+
+namespace memory
+{
+
+class DRAMSys : public AbstractMemory
+{
+ typedef DRAMSysParams Params;
+ sc_gem5::TlmTargetWrapper<32> tlmWrapper;
+
+ public:
+ DRAMSys(Params const& params) :
+ AbstractMemory(params),
+ tlmWrapper(dramSysWrapper.tSocket, params.name + ".tlm",
InvalidPortID),
+ config(DRAMSysConfiguration::from_path(
+ params.configuration,
+ params.resource_directory)),
+ dramSysWrapper(params.name.c_str(), config, params.recordable)
+ {}
+
+ gem5::Port &
+ getPort(const std::string &if_name, PortID idx) override {
+ return tlmWrapper;
+ }
+
+ private:
+ DRAMSysConfiguration::Configuration config;
+ DRAMSysWrapper dramSysWrapper;
+};
+
+} // namespace memory
+} // namespace gem5
+
+#endif // __MEM_DRAMSYS_HH__
diff --git a/src/mem/dramsys_wrapper.cc b/src/mem/dramsys_wrapper.cc
index 349e953..38d60fc 100644
--- a/src/mem/dramsys_wrapper.cc
+++ b/src/mem/dramsys_wrapper.cc
@@ -34,14 +34,14 @@
namespace memory
{
-std::shared_ptr<DRAMSys>
+std::shared_ptr<::DRAMSys>
DRAMSysWrapper::instantiateDRAMSys(bool recordable,
DRAMSysConfiguration::Configuration
const& config)
{
return recordable ?
- std::make_shared<DRAMSysRecordable>("DRAMSys", config) :
- std::make_shared<DRAMSys>("DRAMSys", config);
+ std::make_shared<::DRAMSysRecordable>("DRAMSys", config) :
+ std::make_shared<::DRAMSys>("DRAMSys", config);
}
tlm::tlm_sync_enum
@@ -60,25 +60,5 @@
return tSocket->nb_transport_bw(payload, phase, bwDelay);
}
-gem5::Port
-&DRAMSysWrapper::gem5_getPort(const std::string &if_name, int idx)
-{
- return wrapper;
-}
-
} // namespace memory
} // namespace gem5
-
-// This "create" method bridges the python configuration and the systemc
-// objects. It instantiates the DRAMSysWrapper object and sets it up using
the
-// parameter values from the config, just like it would for a SimObject.
The
-// systemc object could accept those parameters however it likes, for
instance
-// through its constructor or by assigning them to a member variable.
-gem5::memory::DRAMSysWrapper *
-gem5::DRAMSysParams::create() const
-{
- using namespace gem5::memory;
-
- DRAMSysWrapper *target = new DRAMSysWrapper(name.c_str(), *this);
- return target;
-}
diff --git a/src/mem/dramsys_wrapper.hh b/src/mem/dramsys_wrapper.hh
index 6aede24..766b653 100644
--- a/src/mem/dramsys_wrapper.hh
+++ b/src/mem/dramsys_wrapper.hh
@@ -33,7 +33,6 @@
#include <memory>
#include "DRAMSysConfiguration.h"
-#include "mem/abstract_mem.hh"
#include "params/DRAMSys.hh"
#include "sim/core.hh"
#include "simulation/DRAMSysRecordable.h"
@@ -50,28 +49,23 @@
namespace memory
{
-class DRAMSysWrapper : public sc_core::sc_module, public AbstractMemory
+class DRAMSysWrapper : public sc_core::sc_module
{
- private:
- typedef DRAMSysParams Params;
+ friend class DRAMSys;
+ private:
tlm_utils::simple_initiator_socket<DRAMSysWrapper> iSocket;
tlm_utils::simple_target_socket<DRAMSysWrapper> tSocket;
- sc_gem5::TlmTargetWrapper<32> wrapper;
- DRAMSysConfiguration::Configuration config;
- std::shared_ptr<DRAMSys> dramsys;
+ std::shared_ptr<::DRAMSys> dramsys;
public:
SC_HAS_PROCESS(DRAMSysWrapper);
- DRAMSysWrapper(sc_core::sc_module_name name, Params const& params) :
+ DRAMSysWrapper(sc_core::sc_module_name name,
+ DRAMSysConfiguration::Configuration const& config,
+ bool recordable) :
sc_core::sc_module(name),
- AbstractMemory(params),
- wrapper(tSocket, params.name + ".tlm", InvalidPortID),
- config(DRAMSysConfiguration::from_path(
- params.configuration,
- params.resource_directory)),
- dramsys(instantiateDRAMSys(params.recordable, config))
+ dramsys(instantiateDRAMSys(recordable, config))
{
tSocket.register_nb_transport_fw(this,
&DRAMSysWrapper::nb_transport_fw);
@@ -87,10 +81,8 @@
});
}
- gem5::Port &gem5_getPort(const std::string &if_name, int idx=-1)
override;
-
private:
- static std::shared_ptr<DRAMSys>
+ static std::shared_ptr<::DRAMSys>
instantiateDRAMSys(bool recordable,
DRAMSysConfiguration::Configuration const& config);
diff --git a/src/python/gem5/components/memory/__init__.py
b/src/python/gem5/components/memory/__init__.py
index 490945b..bd62f0b 100644
--- a/src/python/gem5/components/memory/__init__.py
+++ b/src/python/gem5/components/memory/__init__.py
@@ -34,4 +34,4 @@
from .multi_channel import DualChannelDDR4_2400
from .multi_channel import DualChannelLPDDR3_1600
from .hbm import HBM2Stack
-from .dramsys import DRAMSysMemCtrl
+from .dramsys import DRAMSysMem
diff --git a/src/python/gem5/components/memory/dramsys.py
b/src/python/gem5/components/memory/dramsys.py
index b533055..ab95548 100644
--- a/src/python/gem5/components/memory/dramsys.py
+++ b/src/python/gem5/components/memory/dramsys.py
@@ -35,20 +35,22 @@
from ..boards.abstract_board import AbstractBoard
from .abstract_memory_system import AbstractMemorySystem
-
from typing import Optional, Tuple, Sequence, List
-class DRAMSysMemCtrl(AbstractMemorySystem):
+class DRAMSysMem(AbstractMemorySystem):
def __init__(
self,
configuration: str,
+ size: str,
resource_directory: str,
recordable: bool,
- size: str,
) -> None:
"""
- :param size: The size of the memory. Has to match the DRAMSys
configuration.
+ :param configuration: Path to the base configuration JSON for
DRAMSys.
+ :param size: Memory size of DRAMSys. Must match the size specified
in JSON configuration.
+ :param resource_directory: Path to the base resource directory for
DRAMSys.
+ :param recordable: Whether the database recording feature of
DRAMSys is enabled.
"""
super().__init__()
self.dramsys = DRAMSys(
@@ -59,7 +61,7 @@
self._size = toMemorySize(size)
self._bridge = Gem5ToTlmBridge32()
- self.dramsys.tlm = self._bridge.tlm
+ self.dramsys.port = self._bridge.tlm
@overrides(AbstractMemorySystem)
def incorporate_memory(self, board: AbstractBoard) -> None:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia409eafc6e94529f887016db043e98e7dd80bf5e
Gerrit-Change-Number: 68218
Gerrit-PatchSet: 1
Gerrit-Owner: Derek C. <christ.de...@gmail.com>
Gerrit-MessageType: newchange
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