[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv,dev: Add PLIC abstract class to support multiple PLIC impl...

[Roger Chang (Gerrit) via gem5-dev]

Roger Chang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/68197?usp=email )

Change subject: arch-riscv,dev: Add PLIC abstract class to support multiple  
PLIC implementation
......................................................................

arch-riscv,dev: Add PLIC abstract class to support multiple PLIC
implementation

We should create PLIC abstract and have common interface to let
HiFive platform send and clear interrupt to variable PLIC

Change-Id: Ic3a2ffc2a2a002540b400c70c85c3495fa838f2a
---
M src/dev/riscv/Plic.py
M src/dev/riscv/SConscript
M src/dev/riscv/plic.cc
M src/dev/riscv/plic.hh
4 files changed, 53 insertions(+), 7 deletions(-)



diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
index 33b6940..3233e0d 100644
--- a/src/dev/riscv/Plic.py
+++ b/src/dev/riscv/Plic.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2021 Huawei International
+# Copyright (c) 2023 Google LLC
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -39,7 +40,21 @@
 from m5.util.fdthelper import *


-class Plic(BasicPioDevice):
+class PlicBase(BasicPioDevice):
+  """
+  This is abstract class of PLIC and
+  define interface to handle received
+  interrupt singal from device
+  """
+  type = "PlicBase"
+  cxx_header = "dev/riscv/plic.hh"
+  cxx_class = "gem5::PlicBase"
+  abstract = True
+
+  pio_size = Param.Addr("PIO Size")
+
+
+class Plic(PlicBase):
     """
     This implementation of PLIC is based on
     the SiFive U54MC datasheet:
@@ -51,7 +66,7 @@
     type = "Plic"
     cxx_header = "dev/riscv/plic.hh"
     cxx_class = "gem5::Plic"
-    pio_size = Param.Addr(0x4000000, "PIO Size")
+    pio_size = 0x4000000
     n_src = Param.Int("Number of interrupt sources")
     n_contexts = Param.Int(
         "Number of interrupt contexts. Usually the number "
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
index af0b96b..6e3376b 100755
--- a/src/dev/riscv/SConscript
+++ b/src/dev/riscv/SConscript
@@ -2,6 +2,7 @@

 # Copyright (c) 2021 Huawei International
 # Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
+# Copyright (c) 2023 Google LLC
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -34,7 +35,7 @@
 SimObject('LupV.py', sim_objects=['LupV'], tags='riscv isa')
 SimObject('Clint.py', sim_objects=['Clint'], tags='riscv isa')
 SimObject('PlicDevice.py', sim_objects=['PlicIntDevice'], tags='riscv isa')
-SimObject('Plic.py', sim_objects=['Plic'], tags='riscv isa')
+SimObject('Plic.py', sim_objects=['PlicBase', 'Plic'], tags='riscv isa')
 SimObject('RTC.py', sim_objects=['RiscvRTC'], tags='riscv isa')
 SimObject('RiscvVirtIOMMIO.py', sim_objects=['RiscvMmioVirtIO'],
     tags='riscv isa')
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index b8f765a..edf0e06 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -45,6 +45,7 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/Plic.hh"
+#include "params/PlicBase.hh"
 #include "sim/system.hh"

 namespace gem5
@@ -53,7 +54,7 @@
 using namespace RiscvISA;

 Plic::Plic(const Params &params) :
-    BasicPioDevice(params, params.pio_size),
+    PlicBase(params),
     system(params.system),
     nSrc(params.n_src),
     nContext(params.n_contexts),
diff --git a/src/dev/riscv/plic.hh b/src/dev/riscv/plic.hh
index d077e73..0b30813 100644
--- a/src/dev/riscv/plic.hh
+++ b/src/dev/riscv/plic.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021 Huawei International
+ * Copyright (c) 2023 Google LLC
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -47,6 +48,7 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/Plic.hh"
+#include "params/PlicBase.hh"
 #include "sim/system.hh"

 namespace gem5
@@ -94,7 +96,21 @@
   std::vector<uint32_t> maxPriority;
 };

-class Plic : public BasicPioDevice
+class PlicBase : public BasicPioDevice
+{
+  public:
+    typedef PlicBaseParams Params;
+    PlicBase(const Params &params) :
+      BasicPioDevice(params, params.pio_size)
+    {}
+
+    /** Interrupt interface to send signal to PLIC */
+    virtual void post(int src_id) = 0;
+    /** Interrupt interface to clear signal to PLIC */
+    virtual void clear(int src_id) = 0;
+};
+
+class Plic : public PlicBase
 {
   // Params
   protected:
@@ -125,8 +141,8 @@
     /**
      * Interrupt interface
      */
-    void post(int src_id);
-    void clear(int src_id);
+    void post(int src_id) override;
+    void clear(int src_id) override;

     /**
      * SimObject functions

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic3a2ffc2a2a002540b400c70c85c3495fa838f2a
Gerrit-Change-Number: 68197
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-MessageType: newchange
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