[AMD Official Use Only - General] This should fix the build: https://gem5-review.googlesource.com/c/public/gem5/+/67977
-Matt -----Original Message----- From: jenkins-no-reply=gem5....@mg.gem5.org <jenkins-no-reply=gem5....@mg.gem5.org> On Behalf Of jenkins-no-reply--- via gem5-dev Sent: Wednesday, February 15, 2023 12:20 AM To: gem5-dev@gem5.org Cc: jenkins-no-re...@gem5.org Subject: [gem5-dev] Build failed in Jenkins: nightly #521 Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding. See <https://jenkins.gem5.org/job/nightly/521/display/redirect?page=changes> Changes: [matthew.poremba] dev-amdgpu: Fix address in POLL_REGMEM SDMA packet [matthew.poremba] arch-vega: Implementing global_atomic_or [matthew.poremba] arch-vega: Implementing global_atomic_smin [matthew.poremba] arch-vega: Implementing global_atomic_smax [matthew.poremba] dev-amdgpu: Update deprecated ports [hungweihsu] dev: add method to set initial register value out of constructor. [rogerycchang] arch-riscv: Fix the behavior of write to status CSR ------------------------------------------ [...truncated 985.31 KB...] [ CXX] VEGA_X86/gpu-compute/register_manager.cc -> .o [ CXX] VEGA_X86/gpu-compute/vector_register_file.cc -> .o [ CXX] VEGA_X86/python/_m5/param_VectorRegisterFile.cc -> .o [ CXX] VEGA_X86/gpu-compute/gpu_exec_context.cc -> .o [ CXX] VEGA_X86/gpu-compute/schedule_stage.cc -> .o [ CXX] VEGA_X86/gpu-compute/exec_stage.cc -> .o [ CXX] VEGA_X86/gpu-compute/lds_state.cc -> .o [ CXX] VEGA_X86/python/_m5/param_ComputeUnit.cc -> .o [ CXX] VEGA_X86/gpu-compute/shader.cc -> .o [ CXX] VEGA_X86/gpu-compute/global_memory_pipeline.cc -> .o [ CXX] VEGA_X86/gpu-compute/comm.cc -> .o [ CXX] VEGA_X86/gpu-compute/register_file.cc -> .o [ CXX] VEGA_X86/gpu-compute/static_register_manager_policy.cc -> .o [ CXX] VEGA_X86/python/_m5/param_ScalarRegisterFile.cc -> .o [ CXX] VEGA_X86/gpu-compute/gpu_dyn_inst.cc -> .o [ CXX] VEGA_X86/gpu-compute/scalar_register_file.cc -> .o [ CXX] VEGA_X86/python/_m5/param_Wavefront.cc -> .o [ CXX] VEGA_X86/gpu-compute/gpu_static_inst.cc -> .o [ CXX] VEGA_X86/gpu-compute/scoreboard_check_stage.cc -> .o [SO Param] m5.objects.TlmBridge, TlmToGem5Bridge32 -> VEGA_X86/python/_m5/param_TlmToGem5Bridge32.cc [ CXX] VEGA_X86/systemc/dt/fx/sc_fxdefs.cc -> .o [ CXX] VEGA_X86/systemc/dt/fx/scfx_mant.cc -> .o [ CXX] VEGA_X86/python/_m5/param_TlmToGem5Bridge32.cc -> .o [ CXX] VEGA_X86/systemc/dt/fx/sc_fxnum.cc -> .o [ CXX] VEGA_X86/systemc/dt/fx/sc_fxnum_observer.cc -> .o [ CXX] VEGA_X86/systemc/dt/fx/scfx_pow10.cc -> .o [ CXX] VEGA_X86/systemc/dt/fx/scfx_rep.cc -> .o [ CXX] VEGA_X86/systemc/dt/fx/sc_fxtype_params.cc -> .o [ CXX] VEGA_X86/systemc/dt/fx/scfx_utils.cc -> .o [ CXX] VEGA_X86/systemc/dt/fx/sc_fxval.cc -> .o [ CXX] VEGA_X86/systemc/dt/fx/sc_fxval_observer.cc -> .o [ CXX] VEGA_X86/systemc/tlm_utils/convenience_socket_bases.cc -> .o [ CXX] VEGA_X86/systemc/tlm_utils/instance_specific_extensions.cc -> .o [ CXX] VEGA_X86/systemc/channel/messages.cc -> .o [ CXX] VEGA_X86/systemc/channel/sc_clock.cc -> .o [ CXX] VEGA_X86/systemc/channel/sc_event_queue.cc -> .o [ CXX] VEGA_X86/systemc/channel/sc_in_resolved.cc -> .o [ CXX] VEGA_X86/systemc/channel/sc_inout_resolved.cc -> .o [ CXX] VEGA_X86/systemc/channel/sc_out_resolved.cc -> .o [ CXX] VEGA_X86/systemc/channel/sc_mutex.cc -> .o [ CXX] VEGA_X86/systemc/channel/sc_semaphore.cc -> .o [ CXX] VEGA_X86/systemc/channel/sc_signal.cc -> .o [ CXX] VEGA_X86/systemc/channel/sc_signal_resolved.cc -> .o [ TRACING] -> VEGA_X86/debug/IntRegs.cc [ CXX] VEGA_X86/debug/IntRegs.cc -> .o [ TRACING] -> VEGA_X86/debug/FloatRegs.cc [ CXX] VEGA_X86/debug/FloatRegs.cc -> .o [ TRACING] -> VEGA_X86/debug/VecRegs.cc [ TRACING] -> VEGA_X86/debug/VecPredRegs.cc [ CXX] VEGA_X86/debug/VecRegs.cc -> .o [ CXX] VEGA_X86/debug/VecPredRegs.cc -> .o [ TRACING] -> VEGA_X86/debug/MatRegs.cc [ TRACING] -> VEGA_X86/debug/CCRegs.cc [ CXX] VEGA_X86/debug/MatRegs.cc -> .o [ TRACING] -> VEGA_X86/debug/MiscRegs.cc [ CXX] VEGA_X86/debug/CCRegs.cc -> .o [ TRACING] -> VEGA_X86/debug/Registers.cc [ TRACING] -> VEGA_X86/debug/MiscRegs.hh [ TRACING] -> VEGA_X86/debug/Registers.hh [ TRACING] -> VEGA_X86/debug/Decoder.cc [ CXX] VEGA_X86/debug/MiscRegs.cc -> .o [ CXX] VEGA_X86/debug/Registers.cc -> .o [ TRACING] -> VEGA_X86/debug/Decoder.hh [ TRACING] -> VEGA_X86/debug/Faults.cc [ CXX] VEGA_X86/debug/Decoder.cc -> .o [ TRACING] -> VEGA_X86/debug/Faults.hh [ TRACING] -> VEGA_X86/debug/TLBVerbose.cc [ CXX] VEGA_X86/arch/amdgpu/common/X86GPUTLB.py.cc -> .o [ CXX] VEGA_X86/debug/Faults.cc -> .o [ TRACING] -> VEGA_X86/debug/TLBVerbose.hh [SO Param] m5.objects.X86GPUTLB, X86GPUTLB -> VEGA_X86/python/_m5/param_X86GPUTLB.cc [ CXX] VEGA_X86/debug/TLBVerbose.cc -> .o [SO Param] m5.objects.X86GPUTLB, TLBCoalescer -> VEGA_X86/python/_m5/param_TLBCoalescer.cc [ TRACING] -> VEGA_X86/debug/PseudoInst.hh [ TRACING] -> VEGA_X86/debug/X86.hh [SO Param] m5.objects.X86GPUTLB, TLBCoalescer -> VEGA_X86/params/TLBCoalescer.hh [ CXX] VEGA_X86/arch/amdgpu/vega/VegaGPUTLB.py.cc -> .o [ CXX] VEGA_X86/python/_m5/param_X86GPUTLB.cc -> .o [SO Param] m5.objects.VegaGPUTLB, VegaPagetableWalker -> VEGA_X86/python/_m5/param_VegaPagetableWalker.cc [ CXX] VEGA_X86/arch/amdgpu/common/tlb.cc -> .o [SO Param] m5.objects.VegaGPUTLB, VegaGPUTLB -> VEGA_X86/python/_m5/param_VegaGPUTLB.cc [SO Param] m5.objects.VegaGPUTLB, VegaTLBCoalescer -> VEGA_X86/python/_m5/param_VegaTLBCoalescer.cc [ CXX] VEGA_X86/arch/amdgpu/vega/faults.cc -> .o [ CXX] VEGA_X86/python/_m5/param_TLBCoalescer.cc -> .o [ CXX] VEGA_X86/python/_m5/param_VegaPagetableWalker.cc -> .o [ CXX] VEGA_X86/arch/amdgpu/common/tlb_coalescer.cc -> .o [ CXX] VEGA_X86/python/_m5/param_VegaGPUTLB.cc -> .o [SO Param] m5.objects.VegaGPUTLB, VegaTLBCoalescer -> VEGA_X86/params/VegaTLBCoalescer.hh [ CXX] VEGA_X86/arch/amdgpu/vega/pagetable.cc -> .o [ CXX] VEGA_X86/arch/amdgpu/vega/pagetable_walker.cc -> .o [ CXX] VEGA_X86/arch/amdgpu/vega/tlb.cc -> .o [ TRACING] -> VEGA_X86/debug/GPUPTWalker.cc [ CXX] VEGA_X86/debug/GPUPTWalker.cc -> .o [ CXX] VEGA_X86/python/_m5/param_VegaTLBCoalescer.cc -> .o [ CXX] VEGA_X86/arch/amdgpu/vega/tlb_coalescer.cc -> .o [ TRACING] -> VEGA_X86/debug/VEGA.hh [ CXX] VEGA_X86/arch/amdgpu/vega/isa.cc -> .o [ CXX] VEGA_X86/arch/amdgpu/vega/insts/op_encodings.cc -> .o [ CXX] VEGA_X86/arch/amdgpu/vega/insts/instructions.cc -> .o [ CXX] VEGA_X86/arch/amdgpu/vega/decoder.cc -> .o build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc: In member function 'virtual void gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN::execute(gem5::GPUDynInstPtr)': build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc:44993:30: error: cannot convert 'gem5::VegaISA::ConstVecOperandU64' {aka 'gem5::VegaISA::VecOperand<long unsigned int, true>'} to 'gem5::VegaISA::ScalarRegU32' {aka 'unsigned int'} 44993 | calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET); | ^~~~ | | | gem5::VegaISA::ConstVecOperandU64 {aka gem5::VegaISA::VecOperand<long unsigned int, true>} In file included from build/VEGA_X86/arch/amdgpu/vega/insts/instructions.hh:37, from build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc:32: build/VEGA_X86/arch/amdgpu/vega/insts/op_encodings.hh:928:57: note: initializing argument 2 of 'void gem5::VegaISA::Inst_FLAT::calcAddr(gem5::GPUDynInstPtr, gem5::VegaISA::ScalarRegU32, gem5::VegaISA::ScalarRegU32, gem5::VegaISA::ScalarRegI32)' 928 | calcAddr(GPUDynInstPtr gpuDynInst, ScalarRegU32 vaddr, | ~~~~~~~~~~~~~^~~~~ build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc: In member function 'virtual void gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX::execute(gem5::GPUDynInstPtr)': build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc:45100:30: error: cannot convert 'gem5::VegaISA::ConstVecOperandU64' {aka 'gem5::VegaISA::VecOperand<long unsigned int, true>'} to 'gem5::VegaISA::ScalarRegU32' {aka 'unsigned int'} 45100 | calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET); | ^~~~ | | | gem5::VegaISA::ConstVecOperandU64 {aka gem5::VegaISA::VecOperand<long unsigned int, true>} In file included from build/VEGA_X86/arch/amdgpu/vega/insts/instructions.hh:37, from build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc:32: build/VEGA_X86/arch/amdgpu/vega/insts/op_encodings.hh:928:57: note: initializing argument 2 of 'void gem5::VegaISA::Inst_FLAT::calcAddr(gem5::GPUDynInstPtr, gem5::VegaISA::ScalarRegU32, gem5::VegaISA::ScalarRegU32, gem5::VegaISA::ScalarRegI32)' 928 | calcAddr(GPUDynInstPtr gpuDynInst, ScalarRegU32 vaddr, | ~~~~~~~~~~~~~^~~~~ build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc: In member function 'virtual void gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR::execute(gem5::GPUDynInstPtr)': build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc:45235:30: error: cannot convert 'gem5::VegaISA::ConstVecOperandU64' {aka 'gem5::VegaISA::VecOperand<long unsigned int, true>'} to 'gem5::VegaISA::ScalarRegU32' {aka 'unsigned int'} 45235 | calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET); | ^~~~ | | | gem5::VegaISA::ConstVecOperandU64 {aka gem5::VegaISA::VecOperand<long unsigned int, true>} In file included from build/VEGA_X86/arch/amdgpu/vega/insts/instructions.hh:37, from build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc:32: build/VEGA_X86/arch/amdgpu/vega/insts/op_encodings.hh:928:57: note: initializing argument 2 of 'void gem5::VegaISA::Inst_FLAT::calcAddr(gem5::GPUDynInstPtr, gem5::VegaISA::ScalarRegU32, gem5::VegaISA::ScalarRegU32, gem5::VegaISA::ScalarRegI32)' 928 | calcAddr(GPUDynInstPtr gpuDynInst, ScalarRegU32 vaddr, | ~~~~~~~~~~~~~^~~~~ Generating LALR tables scons: *** [build/VEGA_X86/arch/amdgpu/vega/insts/instructions.o] Error 1 [ CXX] VEGA_X86/arch/amdgpu/vega/insts/gpu_static_inst.cc -> .o [ CXX] VEGA_X86/arch/amdgpu/vega/registers.cc -> .o [ TRACING] -> VEGA_X86/debug/VEGA.cc [ CXX] VEGA_X86/debug/VEGA.cc -> .o [ CXX] VEGA_X86/arch/generic/htm.cc -> .o [ CXX] VEGA_X86/arch/generic/mmu.cc -> .o [ CXX] VEGA_X86/arch/generic/BaseInterrupts.py.cc -> .o [SO Param] m5.objects.BaseInterrupts, BaseInterrupts -> VEGA_X86/python/_m5/param_BaseInterrupts.cc [ CXX] VEGA_X86/python/_m5/param_BaseInterrupts.cc -> .o [ CXX] VEGA_X86/arch/generic/BaseISA.py.cc -> .o [SO Param] m5.objects.BaseISA, BaseISA -> VEGA_X86/python/_m5/param_BaseISA.cc [ CXX] VEGA_X86/arch/generic/BaseMMU.py.cc -> .o [ CXX] VEGA_X86/python/_m5/param_BaseISA.cc -> .o [SO Param] m5.objects.BaseMMU, BaseMMU -> VEGA_X86/python/_m5/param_BaseMMU.cc [ CXX] VEGA_X86/arch/generic/BaseTLB.py.cc -> .o [ CXX] VEGA_X86/python/_m5/param_BaseMMU.cc -> .o [SO Param] m5.objects.BaseTLB, BaseTLB -> VEGA_X86/python/_m5/param_BaseTLB.cc [ENUM STR] m5.objects.BaseTLB, TypeTLB -> VEGA_X86/enums/TypeTLB.cc [ CXX] VEGA_X86/arch/generic/InstDecoder.py.cc -> .o [SO Param] m5.objects.InstDecoder, InstDecoder -> VEGA_X86/python/_m5/param_InstDecoder.cc [ CXX] VEGA_X86/enums/TypeTLB.cc -> .o [ CXX] VEGA_X86/python/_m5/param_BaseTLB.cc -> .o [ TRACING] -> VEGA_X86/debug/PageTableWalker.cc [ CXX] VEGA_X86/python/_m5/param_InstDecoder.cc -> .o [ TRACING] -> VEGA_X86/debug/PageTableWalker.hh [ CXX] VEGA_X86/debug/PageTableWalker.cc -> .o [ TRACING] -> VEGA_X86/debug/TLB.cc [ TRACING] -> VEGA_X86/debug/TLB.hh [ CXX] VEGA_X86/debug/TLB.cc -> .o [ CXX] VEGA_X86/arch/generic/decoder.cc -> .o [ CXX] VEGA_X86/arch/x86/cpuid.cc -> .o [ TRACING] -> VEGA_X86/debug/Decode.hh [SO Param] m5.objects.X86Decoder, X86Decoder -> VEGA_X86/params/X86Decoder.hh [ CXX] VEGA_X86/arch/x86/emulenv.cc -> .o build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc: In member function 'virtual void gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN::execute(gem5::GPUDynInstPtr)': build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc:44993:30: error: cannot convert 'gem5::VegaISA::ConstVecOperandU64' {aka 'gem5::VegaISA::VecOperand<long unsigned int, true>'} to 'gem5::VegaISA::ScalarRegU32' {aka 'unsigned int'} 44993 | calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET); | ^~~~ | | | gem5::VegaISA::ConstVecOperandU64 {aka gem5::VegaISA::VecOperand<long unsigned int, true>} In file included from build/VEGA_X86/arch/amdgpu/vega/insts/instructions.hh:37, from build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc:32: build/VEGA_X86/arch/amdgpu/vega/insts/op_encodings.hh:928:57: note: initializing argument 2 of 'void gem5::VegaISA::Inst_FLAT::calcAddr(gem5::GPUDynInstPtr, gem5::VegaISA::ScalarRegU32, gem5::VegaISA::ScalarRegU32, gem5::VegaISA::ScalarRegI32)' 928 | calcAddr(GPUDynInstPtr gpuDynInst, ScalarRegU32 vaddr, | ~~~~~~~~~~~~~^~~~~ build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc: In member function 'virtual void gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX::execute(gem5::GPUDynInstPtr)': build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc:45100:30: error: cannot convert 'gem5::VegaISA::ConstVecOperandU64' {aka 'gem5::VegaISA::VecOperand<long unsigned int, true>'} to 'gem5::VegaISA::ScalarRegU32' {aka 'unsigned int'} 45100 | calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET); | ^~~~ | | | gem5::VegaISA::ConstVecOperandU64 {aka gem5::VegaISA::VecOperand<long unsigned int, true>} In file included from build/VEGA_X86/arch/amdgpu/vega/insts/instructions.hh:37, from build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc:32: build/VEGA_X86/arch/amdgpu/vega/insts/op_encodings.hh:928:57: note: initializing argument 2 of 'void gem5::VegaISA::Inst_FLAT::calcAddr(gem5::GPUDynInstPtr, gem5::VegaISA::ScalarRegU32, gem5::VegaISA::ScalarRegU32, gem5::VegaISA::ScalarRegI32)' 928 | calcAddr(GPUDynInstPtr gpuDynInst, ScalarRegU32 vaddr, | ~~~~~~~~~~~~~^~~~~ build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc: In member function 'virtual void gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR::execute(gem5::GPUDynInstPtr)': build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc:45235:30: error: cannot convert 'gem5::VegaISA::ConstVecOperandU64' {aka 'gem5::VegaISA::VecOperand<long unsigned int, true>'} to 'gem5::VegaISA::ScalarRegU32' {aka 'unsigned int'} 45235 | calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET); | ^~~~ | | | gem5::VegaISA::ConstVecOperandU64 {aka gem5::VegaISA::VecOperand<long unsigned int, true>} In file included from build/VEGA_X86/arch/amdgpu/vega/insts/instructions.hh:37, from build/VEGA_X86/arch/amdgpu/vega/insts/instructions.cc:32: build/VEGA_X86/arch/amdgpu/vega/insts/op_encodings.hh:928:57: note: initializing argument 2 of 'void gem5::VegaISA::Inst_FLAT::calcAddr(gem5::GPUDynInstPtr, gem5::VegaISA::ScalarRegU32, gem5::VegaISA::ScalarRegU32, gem5::VegaISA::ScalarRegI32)' 928 | calcAddr(GPUDynInstPtr gpuDynInst, ScalarRegU32 vaddr, | ~~~~~~~~~~~~~^~~~~ [ISA DESC] VEGA_X86/arch/x86/isa/main.isa -> generated/decoder-g.cc.inc, generated/decoder-ns.cc.inc, generated/decode-method.cc.inc, generated/decoder.hh, generated/decoder-g.hh.inc, generated/decoder-ns.hh.inc, generated/exec-g.cc.inc, generated/exec-ns.cc.inc, generated/decoder.cc, generated/inst-constrs.cc, generated/generic_cpu_exec.cc [ CXX] VEGA_X86/arch/x86/decoder.cc -> .o [ CXX] VEGA_X86/arch/x86/decoder_tables.cc -> .o [SO Param] m5.objects.X86MMU, X86MMU -> VEGA_X86/params/X86MMU.hh [ TRACING] -> VEGA_X86/debug/ACPI.hh [SO Param] m5.objects.X86FsWorkload, X86FsWorkload -> VEGA_X86/params/X86FsWorkload.hh [SO Param] m5.objects.ACPI, X86ACPIMadt -> VEGA_X86/params/X86ACPIMadt.hh Generating LALR tables scons: *** [build/VEGA_X86/arch/amdgpu/vega/insts/instructions.o] Error 1 scons: building terminated because of errors. Traceback (most recent call last): File "/nobackup/jenkins/workspace/nightly/tests/../ext/testlib/runner.py", line 205, in setup fixture.setup(testitem) File "/nobackup/jenkins/workspace/nightly/tests/gem5/fixture.py", line 133, in setup self._setup(testitem) File "/nobackup/jenkins/workspace/nightly/tests/gem5/fixture.py", line 183, in _setup log_call(log.test_log, command, time=None, stderr=sys.stderr) File "/nobackup/jenkins/workspace/nightly/tests/../ext/testlib/helper.py", line 205, in log_call raise subprocess.CalledProcessError(retval, cmdstr) subprocess.CalledProcessError: Command 'scons -C /nobackup/jenkins/workspace/nightly -j 24 --ignore-style --no-compress-debug /nobackup/jenkins/workspace/nightly/build/VEGA_X86/gem5.opt' returned non-zero exit status 2. Exception raised while setting up fixture for Test Library =============================== No testing done ================================ Traceback (most recent call last): File "/nobackup/jenkins/workspace/nightly/tests/./main.py", line 25, in <module> sys.exit(testlib()) File "/nobackup/jenkins/workspace/nightly/tests/../ext/testlib/main.py", line 331, in main result = globals()['do_'+configuration.config.command]() File "/nobackup/jenkins/workspace/nightly/tests/../ext/testlib/main.py", line 303, in do_run return run_schedule(test_schedule, log_handler) File "/nobackup/jenkins/workspace/nightly/tests/../ext/testlib/main.py", line 277, in run_schedule log_handler.finish_testing() File "/nobackup/jenkins/workspace/nightly/tests/../ext/testlib/main.py", line 68, in finish_testing self.result_handler.close() File "/nobackup/jenkins/workspace/nightly/tests/../ext/testlib/handlers.py", line 164, in close self._save() File "/nobackup/jenkins/workspace/nightly/tests/../ext/testlib/handlers.py", line 156, in _save result.JUnitSavedResults.save( File "/nobackup/jenkins/workspace/nightly/tests/../ext/testlib/result.py", line 341, in save results = JUnitTestSuites(results) File "/nobackup/jenkins/workspace/nightly/tests/../ext/testlib/result.py", line 239, in __init__ self.attributes.append(self.result_attribute(result, File "/nobackup/jenkins/workspace/nightly/tests/../ext/testlib/result.py", line 247, in result_attribute return XMLAttribute(self.result_map[result], count) KeyError: 0 Build step 'Execute shell' marked build as failure Archiving artifacts _______________________________________________ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org _______________________________________________ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
