Roger Chang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67897?usp=email )
Change subject: arch-riscv: Fix the behavior of write to status CSR
......................................................................
arch-riscv: Fix the behavior of write to status CSR
According to RISC V spec Volumn I, Section 11.1, the CSR will be
written only if RS1 != 0 or imm != 0. However, after the change
of CL(https://gem5-review.googlesource.com/c/public/gem5/+/67717),
it will cause IllegalInstFault to write status CSR if we don't
change the data.
Example of Instruction Fault for mstatus
```
addi a5, zero, 8
csrc mstatus, a5
```
It will cause instruction fault if mstatus value is 0 due to
"newdata_all == olddata_all". We can just simply check if
the data value is changed out of mask.
Change-Id: Iab4ce7ac646a9105dc04e69c24d084572e28ebab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67897
Reviewed-by: Yu-hsin Wang <yuhsi...@google.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/formats/standard.isa
2 files changed, 34 insertions(+), 3 deletions(-)
Approvals:
Yu-hsin Wang: Looks good to me, approved
kokoro: Regressions pass
Jason Lowe-Power: Looks good to me, approved
diff --git a/src/arch/riscv/insts/standard.hh
b/src/arch/riscv/insts/standard.hh
index afcfd7a..2dfe73a 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -111,7 +111,7 @@
strcmp(mnemonic, "csrrc") == 0 ||
strcmp(mnemonic, "csrrsi") == 0 ||
strcmp(mnemonic, "csrrci") == 0 ){
- if (RS1 == 0) {
+ if (RS1 == 0 || uimm == 0) {
write = false;
}
}
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 1bd431a..c94a0bc 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -358,7 +358,7 @@
%(op_decl)s;
%(op_rd)s;
- RegVal data = 0, olddata = 0;
+ RegVal data = 0, olddata = 0, nonmaskdata = 0;
auto lowestAllowedMode = (PrivilegeMode)bits(csr, 9, 8);
auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
if (pm < lowestAllowedMode) {
@@ -397,6 +397,7 @@
%(code)s;
+ nonmaskdata = data & ~maskVal;
data &= maskVal;
if (write) {
if (bits(csr, 11, 10) == 0x3) {
@@ -419,7 +420,7 @@
case CSR_SIP: case CSR_SIE:
case CSR_UIP: case CSR_UIE:
case CSR_MSTATUS: case CSR_SSTATUS: case CSR_USTATUS:
- if (newdata_all != olddata_all) {
+ if (nonmaskdata == 0) {
xc->setMiscReg(midx, newdata_all);
} else {
return std::make_shared<IllegalInstFault>(
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iab4ce7ac646a9105dc04e69c24d084572e28ebab
Gerrit-Change-Number: 67897
Gerrit-PatchSet: 2
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-Reviewer: Hoa Nguyen <hoangu...@ucdavis.edu>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Roger Chang <rogerycch...@google.com>
Gerrit-Reviewer: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Earl Ou <shunhsin...@google.com>
Gerrit-CC: chengyong zhong <zhongc...@gmail.com>
Gerrit-MessageType: merged
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