Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67677?usp=email )
Change subject: arch-riscv: Fix incorrect trap value of instruction fault
......................................................................
arch-riscv: Fix incorrect trap value of instruction fault
As we add rv_type bit in machInst at 62, It will get the machine
code with rv_type specification if we just return machInst. We
only need return machine code for handling instruction fault.
Change-Id: I9dd7a25047d4a13df5b47dc9e422345ba44b7b09
---
M src/arch/riscv/faults.hh
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index e664767..f687fd6 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -173,7 +173,7 @@
: RiscvFault(n, FaultType::OTHERS, INST_ILLEGAL), _inst(inst)
{}
- RegVal trap_value() const override { return _inst; }
+ RegVal trap_value() const override { return bits(_inst, 31, 0); }
};
class UnknownInstFault : public InstFault
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9dd7a25047d4a13df5b47dc9e422345ba44b7b09
Gerrit-Change-Number: 67677
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-MessageType: newchange
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