Gabriel B. has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67661?usp=email )
Change subject: mem-ruby: Fix of an address bug in MESI_Two_Level-dir.sm
......................................................................
mem-ruby: Fix of an address bug in MESI_Two_Level-dir.sm
Physical access address and line address were mixed up in
qw_queueMemoryWBRequest_partial
Change-Id: I0b238ffc59d2bb3de221d96905c75b7616eac964
---
M src/mem/ruby/protocol/MESI_Two_Level-dir.sm
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
b/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
index aa61424..4eca48f 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
@@ -365,7 +365,7 @@
desc="Queue off-chip writeback request") {
peek(requestNetwork_in, RequestMsg) {
enqueue(memQueue_out, MemoryMsg, to_mem_ctrl_latency) {
- out_msg.addr := address;
+ out_msg.addr := tbe.PhysicalAddress;
out_msg.Type := MemoryRequestType:MEMORY_WB;
out_msg.Sender := machineID;
out_msg.MessageSize := MessageSizeType:Writeback_Data;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0b238ffc59d2bb3de221d96905c75b7616eac964
Gerrit-Change-Number: 67661
Gerrit-PatchSet: 1
Gerrit-Owner: Gabriel B. <gabriel.bus...@arteris.com>
Gerrit-MessageType: newchange
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