See <https://jenkins.gem5.org/job/nightly/493/display/redirect?page=changes>
Changes: [Giacomo Travaglini] arch-arm: Replace Loader with loader namespace in SME code [gabriel.busnot] python: Fix deprecated decorator ------------------------------------------ [...truncated 1.30 MB...] [ TRACING] -> ALL_MSI/debug/TageSCL.cc [ CXX] ALL_MSI/cpu/minor/BaseMinorCPU.py.cc -> .o [SO Param] m5.objects.BaseMinorCPU, MinorOpClass -> ALL_MSI/python/_m5/param_MinorOpClass.cc [ CXX] ALL_MSI/debug/TageSCL.cc -> .o [SO Param] m5.objects.BaseMinorCPU, MinorOpClassSet -> ALL_MSI/python/_m5/param_MinorOpClassSet.cc [SO Param] m5.objects.BaseMinorCPU, MinorFUTiming -> ALL_MSI/python/_m5/param_MinorFUTiming.cc [SO Param] m5.objects.BaseMinorCPU, MinorFU -> ALL_MSI/python/_m5/param_MinorFU.cc [SO Param] m5.objects.BaseMinorCPU, MinorFUPool -> ALL_MSI/python/_m5/param_MinorFUPool.cc [SO Param] m5.objects.BaseMinorCPU, MinorOpClass -> ALL_MSI/params/MinorOpClass.hh [SO Param] m5.objects.BaseMinorCPU, MinorFU -> ALL_MSI/params/MinorFU.hh [SO Param] m5.objects.BaseMinorCPU, MinorOpClassSet -> ALL_MSI/params/MinorOpClassSet.hh [SO Param] m5.objects.BaseMinorCPU, MinorFUTiming -> ALL_MSI/params/MinorFUTiming.hh [SO Param] m5.objects.BaseMinorCPU, MinorFUPool -> ALL_MSI/params/MinorFUPool.hh [ TRACING] -> ALL_MSI/debug/MinorTrace.hh [SO Param] m5.objects.BaseMinorCPU, BaseMinorCPU -> ALL_MSI/python/_m5/param_BaseMinorCPU.cc [ENUM STR] m5.objects.BaseMinorCPU, ThreadPolicy -> ALL_MSI/enums/ThreadPolicy.cc [ CXX] ALL_MSI/cpu/minor/activity.cc -> .o [ TRACING] -> ALL_MSI/debug/MinorCPU.hh [ENUMDECL] m5.objects.BaseMinorCPU, ThreadPolicy -> ALL_MSI/enums/ThreadPolicy.hh [SO Param] m5.objects.BaseMinorCPU, BaseMinorCPU -> ALL_MSI/params/BaseMinorCPU.hh [ TRACING] -> ALL_MSI/debug/MinorExecute.hh [ TRACING] -> ALL_MSI/debug/MinorInterrupt.hh [ TRACING] -> ALL_MSI/debug/MinorMem.hh [ CXX] ALL_MSI/cpu/minor/dyn_inst.cc -> .o [ CXX] ALL_MSI/python/_m5/param_MinorOpClassSet.cc -> .o [ CXX] ALL_MSI/python/_m5/param_MinorOpClass.cc -> .o [ CXX] ALL_MSI/python/_m5/param_MinorFUPool.cc -> .o [ CXX] ALL_MSI/python/_m5/param_MinorFU.cc -> .o [ CXX] ALL_MSI/python/_m5/param_MinorFUTiming.cc -> .o [ TRACING] -> ALL_MSI/debug/MinorTiming.hh [ CXX] ALL_MSI/cpu/minor/pipe_data.cc -> .o [ CXX] ALL_MSI/enums/ThreadPolicy.cc -> .o [ CXX] ALL_MSI/cpu/minor/fetch1.cc -> .o [ CXX] ALL_MSI/cpu/minor/func_unit.cc -> .o [ CXX] ALL_MSI/cpu/minor/execute.cc -> .o [ CXX] ALL_MSI/python/_m5/param_BaseMinorCPU.cc -> .o [ CXX] ALL_MSI/cpu/minor/decode.cc -> .o [ CXX] ALL_MSI/cpu/minor/cpu.cc -> .o [ CXX] ALL_MSI/cpu/minor/lsq.cc -> .o [ CXX] ALL_MSI/cpu/minor/fetch2.cc -> .o [ CXX] ALL_MSI/cpu/minor/pipeline.cc -> .o [ TRACING] -> ALL_MSI/debug/MinorScoreboard.hh [ CXX] ALL_MSI/cpu/minor/scoreboard.cc -> .o [ CXX] ALL_MSI/cpu/minor/stats.cc -> .o [ TRACING] -> ALL_MSI/debug/MinorCPU.cc [ CXX] ALL_MSI/debug/MinorCPU.cc -> .o [ TRACING] -> ALL_MSI/debug/MinorExecute.cc [ CXX] ALL_MSI/debug/MinorExecute.cc -> .o [ TRACING] -> ALL_MSI/debug/MinorInterrupt.cc [ CXX] ALL_MSI/debug/MinorInterrupt.cc -> .o [ TRACING] -> ALL_MSI/debug/MinorMem.cc [ CXX] ALL_MSI/debug/MinorMem.cc -> .o [ TRACING] -> ALL_MSI/debug/MinorScoreboard.cc [ CXX] ALL_MSI/debug/MinorScoreboard.cc -> .o [ TRACING] -> ALL_MSI/debug/MinorTrace.cc [ CXX] ALL_MSI/debug/MinorTrace.cc -> .o [ TRACING] -> ALL_MSI/debug/MinorTiming.cc [ CXX] ALL_MSI/debug/MinorTiming.cc -> .o [ TRACING] -> ALL_MSI/debug/Minor.cc [ CXX] ALL_MSI/cpu/minor/MinorCPU.py.cc -> .o [ TRACING] -> ALL_MSI/debug/Minor.hh [ CXX] ALL_MSI/debug/Minor.cc -> .o [ CXX] ALL_MSI/cpu/o3/FUPool.py.cc -> .o [SO Param] m5.objects.FUPool, FUPool -> ALL_MSI/python/_m5/param_FUPool.cc [SO Param] m5.objects.FUPool, FUPool -> ALL_MSI/params/FUPool.hh [ CXX] ALL_MSI/cpu/o3/FuncUnitConfig.py.cc -> .o [ CXX] ALL_MSI/cpu/o3/BaseO3CPU.py.cc -> .o [ CXX] ALL_MSI/python/_m5/param_FUPool.cc -> .o [SO Param] m5.objects.BaseO3CPU, BaseO3CPU -> ALL_MSI/python/_m5/param_BaseO3CPU.cc [ENUM STR] m5.objects.BaseO3CPU, SMTFetchPolicy -> ALL_MSI/enums/SMTFetchPolicy.cc [ENUMDECL] m5.objects.BaseO3CPU, CommitPolicy -> ALL_MSI/enums/CommitPolicy.hh [ENUMDECL] m5.objects.BaseO3CPU, SMTFetchPolicy -> ALL_MSI/enums/SMTFetchPolicy.hh [ENUMDECL] m5.objects.BaseO3CPU, SMTQueuePolicy -> ALL_MSI/enums/SMTQueuePolicy.hh [SO Param] m5.objects.BaseO3CPU, BaseO3CPU -> ALL_MSI/params/BaseO3CPU.hh [ TRACING] -> ALL_MSI/debug/LSQUnit.hh [ TRACING] -> ALL_MSI/debug/IEW.hh [ CXX] ALL_MSI/enums/SMTFetchPolicy.cc -> .o [ TRACING] -> ALL_MSI/debug/Scoreboard.hh [ TRACING] -> ALL_MSI/debug/MemDepUnit.hh [ENUM STR] m5.objects.BaseO3CPU, SMTQueuePolicy -> ALL_MSI/enums/SMTQueuePolicy.cc [ENUM STR] m5.objects.BaseO3CPU, CommitPolicy -> ALL_MSI/enums/CommitPolicy.cc [ TRACING] -> ALL_MSI/debug/CommitRate.hh [ CXX] ALL_MSI/python/_m5/param_BaseO3CPU.cc -> .o [ TRACING] -> ALL_MSI/debug/O3CPU.hh [ CXX] ALL_MSI/cpu/o3/decode.cc -> .o [ CXX] ALL_MSI/cpu/o3/commit.cc -> .o [ CXX] ALL_MSI/cpu/o3/cpu.cc -> .o [ TRACING] -> ALL_MSI/debug/IQ.hh [ CXX] ALL_MSI/cpu/o3/dyn_inst.cc -> .o [ CXX] ALL_MSI/cpu/o3/fetch.cc -> .o [ CXX] ALL_MSI/enums/SMTQueuePolicy.cc -> .o [ CXX] ALL_MSI/enums/CommitPolicy.cc -> .o [ CXX] ALL_MSI/cpu/o3/free_list.cc -> .o [ CXX] ALL_MSI/cpu/o3/fu_pool.cc -> .o [ CXX] ALL_MSI/cpu/o3/iew.cc -> .o [ CXX] ALL_MSI/cpu/o3/inst_queue.cc -> .o [ TRACING] -> ALL_MSI/debug/LSQ.hh [ TRACING] -> ALL_MSI/debug/Writeback.hh [ CXX] ALL_MSI/cpu/o3/lsq_unit.cc -> .o [ CXX] ALL_MSI/cpu/o3/lsq.cc -> .o [ CXX] ALL_MSI/cpu/o3/mem_dep_unit.cc -> .o [ CXX] ALL_MSI/cpu/o3/regfile.cc -> .o [ TRACING] -> ALL_MSI/debug/Rename.hh [ CXX] ALL_MSI/cpu/o3/rename.cc -> .o [ CXX] ALL_MSI/cpu/o3/rename_map.cc -> .o [ TRACING] -> ALL_MSI/debug/ROB.hh [ CXX] ALL_MSI/cpu/o3/rob.cc -> .o [ CXX] ALL_MSI/cpu/o3/scoreboard.cc -> .o [ TRACING] -> ALL_MSI/debug/StoreSet.hh [ CXX] ALL_MSI/cpu/o3/store_set.cc -> .o [ CXX] ALL_MSI/cpu/o3/thread_context.cc -> .o [ CXX] ALL_MSI/cpu/o3/thread_state.cc -> .o [ TRACING] -> ALL_MSI/debug/CommitRate.cc [ TRACING] -> ALL_MSI/debug/IEW.cc [ CXX] ALL_MSI/debug/CommitRate.cc -> .o [ CXX] ALL_MSI/debug/IEW.cc -> .o [ TRACING] -> ALL_MSI/debug/IQ.cc [ CXX] ALL_MSI/debug/IQ.cc -> .o [ TRACING] -> ALL_MSI/debug/LSQ.cc [ CXX] ALL_MSI/debug/LSQ.cc -> .o [ TRACING] -> ALL_MSI/debug/LSQUnit.cc [ CXX] ALL_MSI/debug/LSQUnit.cc -> .o [ TRACING] -> ALL_MSI/debug/MemDepUnit.cc [ CXX] ALL_MSI/debug/MemDepUnit.cc -> .o [ TRACING] -> ALL_MSI/debug/O3CPU.cc [ CXX] ALL_MSI/debug/O3CPU.cc -> .o [ TRACING] -> ALL_MSI/debug/ROB.cc [ TRACING] -> ALL_MSI/debug/Rename.cc [ CXX] ALL_MSI/debug/ROB.cc -> .o [ TRACING] -> ALL_MSI/debug/Scoreboard.cc [ CXX] ALL_MSI/debug/Rename.cc -> .o [ CXX] ALL_MSI/debug/Scoreboard.cc -> .o [ TRACING] -> ALL_MSI/debug/StoreSet.cc [ CXX] ALL_MSI/debug/StoreSet.cc -> .o [ TRACING] -> ALL_MSI/debug/Writeback.cc [ TRACING] -> ALL_MSI/debug/O3CPUAll.cc [ CXX] ALL_MSI/debug/Writeback.cc -> .o [ CXX] ALL_MSI/cpu/o3/BaseO3Checker.py.cc -> .o [SO Param] m5.objects.BaseO3Checker, BaseO3Checker -> ALL_MSI/python/_m5/param_BaseO3Checker.cc [ TRACING] -> ALL_MSI/debug/O3CPUAll.hh [ CXX] ALL_MSI/debug/O3CPUAll.cc -> .o [ CXX] ALL_MSI/cpu/o3/checker.cc -> .o [ CXX] ALL_MSI/cpu/o3/O3CPU.py.cc -> .o [SO Param] m5.objects.BaseO3Checker, BaseO3Checker -> ALL_MSI/params/BaseO3Checker.hh [ CXX] ALL_MSI/cpu/o3/O3Checker.py.cc -> .o [ CXX] ALL_MSI/cpu/o3/probe/SimpleTrace.py.cc -> .o [ CXX] ALL_MSI/python/_m5/param_BaseO3Checker.cc -> .o [SO Param] m5.objects.SimpleTrace, SimpleTrace -> ALL_MSI/python/_m5/param_SimpleTrace.cc [ TRACING] -> ALL_MSI/debug/SimpleTrace.hh [SO Param] m5.objects.SimpleTrace, SimpleTrace -> ALL_MSI/params/SimpleTrace.hh [ TRACING] -> ALL_MSI/debug/SimpleTrace.cc [ CXX] ALL_MSI/cpu/o3/probe/ElasticTrace.py.cc -> .o [SO Param] m5.objects.ElasticTrace, ElasticTrace -> ALL_MSI/python/_m5/param_ElasticTrace.cc [ TRACING] -> ALL_MSI/debug/ElasticTrace.hh [SO Param] m5.objects.ElasticTrace, ElasticTrace -> ALL_MSI/params/ElasticTrace.hh [ PROTOC] ALL_MSI/proto/inst_dep_record.proto -> ALL_MSI/proto/inst_dep_record.pb.cc, ALL_MSI/proto/inst_dep_record.pb.h [ PROTOC] ALL_MSI/proto/packet.proto -> ALL_MSI/proto/packet.pb.cc, ALL_MSI/proto/packet.pb.h [ TRACING] -> ALL_MSI/debug/ElasticTrace.cc [ CXX] ALL_MSI/cpu/trace/TraceCPU.py.cc -> .o [SO Param] m5.objects.TraceCPU, TraceCPU -> ALL_MSI/python/_m5/param_TraceCPU.cc [ TRACING] -> ALL_MSI/debug/TraceCPUData.hh [ TRACING] -> ALL_MSI/debug/TraceCPUInst.hh [SO Param] m5.objects.TraceCPU, TraceCPU -> ALL_MSI/params/TraceCPU.hh [ TRACING] -> ALL_MSI/debug/TraceCPUData.cc [ TRACING] -> ALL_MSI/debug/TraceCPUInst.cc [ CXX] ALL_MSI/cpu/testers/directedtest/RubyDirectedTester.py.cc -> .o [SO Param] m5.objects.RubyDirectedTester, DirectedGenerator -> ALL_MSI/python/_m5/param_DirectedGenerator.cc [ CXX] ALL_MSI/debug/SimpleTrace.cc -> .o [SO Param] m5.objects.RubyDirectedTester, SeriesRequestGenerator -> ALL_MSI/python/_m5/param_SeriesRequestGenerator.cc [SO Param] m5.objects.RubyDirectedTester, InvalidateGenerator -> ALL_MSI/python/_m5/param_InvalidateGenerator.cc [SO Param] m5.objects.RubyDirectedTester, RubyDirectedTester -> ALL_MSI/python/_m5/param_RubyDirectedTester.cc [ CXX] ALL_MSI/debug/ElasticTrace.cc -> .o [ TRACING] -> ALL_MSI/debug/DirectedTest.hh [ CXX] ALL_MSI/cpu/o3/probe/simple_trace.cc -> .o [ CXX] ALL_MSI/python/_m5/param_SimpleTrace.cc -> .o [ CXX] ALL_MSI/debug/TraceCPUInst.cc -> .o [ CXX] ALL_MSI/debug/TraceCPUData.cc -> .o [SO Param] m5.objects.RubyDirectedTester, DirectedGenerator -> ALL_MSI/params/DirectedGenerator.hh [SO Param] m5.objects.RubyDirectedTester, RubyDirectedTester -> ALL_MSI/params/RubyDirectedTester.hh [ CXX] ALL_MSI/cpu/o3/probe/elastic_trace.cc -> .o [ CXX] ALL_MSI/python/_m5/param_ElasticTrace.cc -> .o [ CXX] ALL_MSI/cpu/trace/trace_cpu.cc -> .o [ CXX] ALL_MSI/python/_m5/param_TraceCPU.cc -> .o [SO Param] m5.objects.RubyDirectedTester, SeriesRequestGenerator -> ALL_MSI/params/SeriesRequestGenerator.hh [SO Param] m5.objects.RubyDirectedTester, InvalidateGenerator -> ALL_MSI/params/InvalidateGenerator.hh [ TRACING] -> ALL_MSI/debug/DirectedTest.cc [ CXX] ALL_MSI/cpu/testers/memtest/MemTest.py.cc -> .o [SO Param] m5.objects.MemTest, MemTest -> ALL_MSI/python/_m5/param_MemTest.cc [ CXX] ALL_MSI/debug/DirectedTest.cc -> .o [ TRACING] -> ALL_MSI/debug/MemTest.hh [SO Param] m5.objects.MemTest, MemTest -> ALL_MSI/params/MemTest.hh [ TRACING] -> ALL_MSI/debug/MemTest.cc [ CXX] ALL_MSI/cpu/testers/rubytest/RubyTester.py.cc -> .o [SO Param] m5.objects.RubyTester, RubyTester -> ALL_MSI/python/_m5/param_RubyTester.cc [ CXX] ALL_MSI/debug/MemTest.cc -> .o [ CXX] ALL_MSI/python/_m5/param_DirectedGenerator.cc -> .o [ CXX] ALL_MSI/python/_m5/param_SeriesRequestGenerator.cc -> .o [ CXX] ALL_MSI/python/_m5/param_InvalidateGenerator.cc -> .o [ CXX] ALL_MSI/cpu/testers/directedtest/InvalidateGenerator.cc -> .o [ CXX] ALL_MSI/python/_m5/param_MemTest.cc -> .o [ CXX] ALL_MSI/cpu/testers/memtest/memtest.cc -> .o [SO Param] m5.objects.RubyTester, RubyTester -> ALL_MSI/params/RubyTester.hh [ CXX] ALL_MSI/cpu/testers/directedtest/SeriesRequestGenerator.cc -> .o [ CXX] ALL_MSI/python/_m5/param_RubyTester.cc -> .o [ CXX] ALL_MSI/cpu/testers/directedtest/DirectedGenerator.cc -> .o [ CXX] ALL_MSI/cpu/testers/directedtest/RubyDirectedTester.cc -> .o [ CXX] ALL_MSI/python/_m5/param_RubyDirectedTester.cc -> .o [ TRACING] -> ALL_MSI/debug/RubyTest.hh [ TRACING] -> ALL_MSI/debug/RubyTest.cc [ CXX] ALL_MSI/cpu/testers/rubytest/Check.cc -> .o [ CXX] ALL_MSI/debug/RubyTest.cc -> .o [ CXX] ALL_MSI/cpu/testers/rubytest/CheckTable.cc -> .o [ CXX] ALL_MSI/cpu/testers/rubytest/RubyTester.cc -> .o [CONFIG H] HAVE_PROTOBUF, 1 -> ALL_MSI/config/have_protobuf.hh [ TRACING] -> ALL_MSI/debug/TrafficGen.hh [ENUMDECL] m5.objects.MemInterface, AddrMap -> ALL_MSI/enums/AddrMap.hh [SO Param] m5.objects.BaseTrafficGen, BaseTrafficGen -> ALL_MSI/params/BaseTrafficGen.hh [ CXX] ALL_MSI/cpu/testers/traffic_gen/exit_gen.cc -> .o [ TRACING] -> ALL_MSI/debug/GUPSGen.hh [SO Param] m5.objects.GUPSGen, GUPSGen -> ALL_MSI/params/GUPSGen.hh [ CXX] ALL_MSI/cpu/testers/traffic_gen/base_gen.cc -> .o [ENUMDECL] m5.objects.BaseTrafficGen, StreamGenType -> ALL_MSI/enums/StreamGenType.hh [ CXX] ALL_MSI/cpu/testers/traffic_gen/gups_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/base.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/dram_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/dram_rot_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/hybrid_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/idle_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/linear_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/nvm_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/random_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/stream_gen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/strided_gen.cc -> .o [ TRACING] -> ALL_MSI/debug/TrafficGen.cc [ CXX] ALL_MSI/debug/TrafficGen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/BaseTrafficGen.py.cc -> .o [SO Param] m5.objects.BaseTrafficGen, BaseTrafficGen -> ALL_MSI/python/_m5/param_BaseTrafficGen.cc [ENUM STR] m5.objects.BaseTrafficGen, StreamGenType -> ALL_MSI/enums/StreamGenType.cc [ TRACING] -> ALL_MSI/debug/GUPSGen.cc [ CXX] ALL_MSI/debug/GUPSGen.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/GUPSGen.py.cc -> .o [ CXX] ALL_MSI/python/_m5/param_BaseTrafficGen.cc -> .o [SO Param] m5.objects.GUPSGen, GUPSGen -> ALL_MSI/python/_m5/param_GUPSGen.cc [SO Param] m5.objects.PyTrafficGen, PyTrafficGen -> ALL_MSI/params/PyTrafficGen.hh [ CXX] ALL_MSI/enums/StreamGenType.cc -> .o [ CXX] ALL_MSI/cpu/testers/traffic_gen/PyTrafficGen.py.cc -> .o time="2023-01-20T02:29:21-06:00" level=error msg="error waiting for container: unexpected EOF" Build step 'Execute shell' marked build as failure Archiving artifacts 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