Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67333?usp=email )
Change subject: arch-arm: Replace Loader with loader namespace in SME code
......................................................................
arch-arm: Replace Loader with loader namespace in SME code
This is fixing our nightly tests [1].
There was a merge conflict between the removal of the Loader namespace
and the SME patches which were still using the old capitalized version
[1]: https://jenkins.gem5.org/job/nightly/491/
Change-Id: I9f709b2fff252ed6fcc76cc984592e713ab53766
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67333
Reviewed-by: Daniel Carvalho <oda...@yahoo.com.br>
Maintainer: Daniel Carvalho <oda...@yahoo.com.br>
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/insts/sme.cc
M src/arch/arm/insts/sme.hh
M src/arch/arm/insts/sve.cc
M src/arch/arm/insts/sve.hh
4 files changed, 43 insertions(+), 22 deletions(-)
Approvals:
kokoro: Regressions pass
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
Richard Cooper: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/insts/sme.cc b/src/arch/arm/insts/sme.cc
index 305d332..43f4579 100644
--- a/src/arch/arm/insts/sme.cc
+++ b/src/arch/arm/insts/sme.cc
@@ -45,7 +45,7 @@
std::string
SmeAddOp::generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab) const
+ const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -61,7 +61,7 @@
std::string
SmeAddVlOp::generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab) const
+ const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -76,7 +76,7 @@
std::string
SmeLd1xSt1xOp::generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab) const
+ const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -94,7 +94,7 @@
std::string
SmeLdrStrOp::generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab) const
+ const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -108,7 +108,7 @@
std::string
SmeMovExtractOp::generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab)
const
+ const loader::SymbolTable *symtab)
const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -124,7 +124,7 @@
std::string
SmeMovInsertOp::generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab)
const
+ const loader::SymbolTable *symtab)
const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -140,7 +140,7 @@
std::string
SmeOPOp::generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab) const
+ const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -158,7 +158,7 @@
std::string
SmeRdsvlOp::generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab) const
+ const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -171,7 +171,7 @@
std::string
SmeZeroOp::generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab) const
+ const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ArmStaticInst::printMnemonic(ss, "", false);
diff --git a/src/arch/arm/insts/sme.hh b/src/arch/arm/insts/sme.hh
index d6cbdde..198ce52 100644
--- a/src/arch/arm/insts/sme.hh
+++ b/src/arch/arm/insts/sme.hh
@@ -63,7 +63,7 @@
{}
std::string generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const override;
+ Addr pc, const loader::SymbolTable *symtab) const override;
};
// Used for the SME ADDSPL/ADDSVL instructions
@@ -82,7 +82,7 @@
{}
std::string generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const override;
+ Addr pc, const loader::SymbolTable *symtab) const override;
};
// Used for SME LD1x/ST1x instrucions
@@ -105,7 +105,7 @@
{}
std::string generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const override;
+ Addr pc, const loader::SymbolTable *symtab) const override;
};
// Used for SME LDR/STR instructions
@@ -124,7 +124,7 @@
{}
std::string generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const override;
+ Addr pc, const loader::SymbolTable *symtab) const override;
};
// Used for SME MOVA (Tile to Vector)
@@ -145,7 +145,7 @@
{}
std::string generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const override;
+ Addr pc, const loader::SymbolTable *symtab) const override;
};
// Used for SME MOVA (Vector to Tile)
@@ -166,7 +166,7 @@
{}
std::string generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const override;
+ Addr pc, const loader::SymbolTable *symtab) const override;
};
// Used for SME output product instructions
@@ -187,7 +187,7 @@
{}
std::string generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const override;
+ Addr pc, const loader::SymbolTable *symtab) const override;
};
// Used for the SME RDSVL instruction
@@ -204,7 +204,7 @@
{}
std::string generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const override;
+ Addr pc, const loader::SymbolTable *symtab) const override;
};
// Used for SME ZERO
@@ -220,7 +220,7 @@
{}
std::string generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const override;
+ Addr pc, const loader::SymbolTable *symtab) const override;
};
} // namespace ArmISA
diff --git a/src/arch/arm/insts/sve.cc b/src/arch/arm/insts/sve.cc
index 9d9c2bc..546074c 100644
--- a/src/arch/arm/insts/sve.cc
+++ b/src/arch/arm/insts/sve.cc
@@ -163,7 +163,7 @@
std::string
SvePselOp::generateDisassembly(Addr pc,
- const Loader::SymbolTable *symtab) const
+ const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -851,7 +851,7 @@
std::string
SveClampOp::generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const
+ Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
diff --git a/src/arch/arm/insts/sve.hh b/src/arch/arm/insts/sve.hh
index 63a59d4..66d82f0 100644
--- a/src/arch/arm/insts/sve.hh
+++ b/src/arch/arm/insts/sve.hh
@@ -199,7 +199,7 @@
{}
std::string generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const override;
+ Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Compare and terminate loop SVE instruction.
@@ -989,7 +989,7 @@
{}
std::string generateDisassembly(
- Addr pc, const Loader::SymbolTable *symtab) const override;
+ Addr pc, const loader::SymbolTable *symtab) const override;
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9f709b2fff252ed6fcc76cc984592e713ab53766
Gerrit-Change-Number: 67333
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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