Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/66931?usp=email )
Change subject: arch-riscv: Correct the IllegalInstFault messege of
instruction c.addi4spn
......................................................................
arch-riscv: Correct the IllegalInstFault messege of instruction
c.addi4spn
In Riscv Manual Volumn I: Unpriviledged ISA section 18.5, c.addi4spn
will not working if imm == 0, not machInst == 0. It is changed in the
[CL](https://gem5-review.git.corp.google.com/c/public/gem5/+/66732), and
here is the additional patch to the CL.
Change-Id: I2a3c9660dc43f1399f68e03c4f59207f869807a0
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index c070392..53d4a4d 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -48,7 +48,7 @@
CIMM8<5:2> << 6;
}}, {{
if (imm == 0)
- return std::make_shared<IllegalInstFault>("zero
instruction",
+ return std::make_shared<IllegalInstFault>("immediate = 0",
machInst);
Rp2 = rvSext(sp + imm);
}}, uint64_t);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2a3c9660dc43f1399f68e03c4f59207f869807a0
Gerrit-Change-Number: 66931
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang <rogerycch...@google.com>
Gerrit-MessageType: newchange
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