Jarvis JIA has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64371?usp=email )
Change subject: mem-ruby: Fix replacement policy in MESI_Two_Level
......................................................................
mem-ruby: Fix replacement policy in MESI_Two_Level
The current MESI_Two_Level protocol's L1 caches updates the MRU information
twice per request on misses -- once when the request reaches Ruby and once
when the miss is returned from another level of the memory hierarchy.
Although this approach does not cause any correctness bugs for replacement
policies like LRU since this request is the LRU in both cases, it does not
work correctly for other policies like SecondChance and LFU, where updating
the information twice (for misses) causes them to devolve to LRU.
Note that this was not directly a problem with Ruby previously, because it
only supported LRU-based policies that were unaffected by this. However,
with the integration of 20879 Ruby now uses the same replacement policies
as Classic (which has additional, non-LRU based replacement policies).
This patch resolves this problem by not updating the MRU information a
second time for the misses. It has been tested and validated with the
replacement policy tests.
Change-Id: I9e7e96a9d6c09f3d6b7daae7115ef091ac3bdc08
---
M src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
index 1a5d0e5..462111f 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
@@ -849,8 +849,6 @@
{
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- L1Icache.setMRU(address);
- L1Dcache.setMRU(address);
sequencer.readCallback(address, cache_entry.DataBlk, true);
}
@@ -867,8 +865,6 @@
{
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- L1Icache.setMRU(address);
- L1Dcache.setMRU(address);
sequencer.writeCallback(address, cache_entry.DataBlk, true);
cache_entry.Dirty := true;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9e7e96a9d6c09f3d6b7daae7115ef091ac3bdc08
Gerrit-Change-Number: 64371
Gerrit-PatchSet: 1
Gerrit-Owner: Jarvis JIA <ji...@wisc.edu>
Gerrit-MessageType: newchange
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